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/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234-p3701.dtsi1 // SPDX-License-Identifier: GPL-2.0
42 dma-controller@2930000 {
46 interrupt-controller@2a40000 {
59 vcc-supply = <&vdd_1v8_hs>;
60 address-width = <8>;
63 read-only;
71 compatible = "jedec,spi-nor";
73 spi-max-frequency = <102000000>;
74 spi-tx-bus-width = <4>;
75 spi-rx-bus-width = <4>;
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H A Dtegra194-p3668.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/mfd/max77620.h>
24 stdout-path = "serial0:115200n8";
31 phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(R, 1) GPIO_ACTIVE_LOW>;
32 phy-handle = <&phy>;
33 phy-mode = "rgmii-id";
36 #address-cells = <1>;
37 #size-cells = <0>;
39 phy: ethernet-phy@0 {
40 compatible = "ethernet-phy-ieee802.3-c22";
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H A Dtegra234-p3767.dtsi1 // SPDX-License-Identifier: GPL-2.0
29 dma-controller@2930000 {
33 interrupt-controller@2a40000 {
46 vcc-supply = <&vdd_1v8_hs>;
47 address-width = <8>;
50 read-only;
58 compatible = "jedec,spi-nor";
60 spi-max-frequency = <102000000>;
61 spi-tx-bus-width = <4>;
62 spi-rx-bus-width = <4>;
[all …]
H A Dtegra194-p2888.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/mfd/max77620.h>
27 stdout-path = "serial0:115200n8";
34 phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>;
35 phy-handle = <&phy>;
36 phy-mode = "rgmii-id";
39 #address-cells = <1>;
40 #size-cells = <0>;
42 phy: ethernet-phy@0 {
43 compatible = "ethernet-phy-ieee802.3-c22";
[all …]
H A Dtegra186-p3509-0000+p3636-0001.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/mfd/max77620.h>
12 compatible = "nvidia,p3509-0000+p3636-0001", "nvidia,tegra186";
30 stdout-path = "serial0:115200n8";
41 phy-reset-gpios = <&gpio_aon TEGRA186_AON_GPIO(AA, 6) GPIO_ACTIVE_LOW>;
42 phy-handle = <&phy>;
43 phy-mode = "rgmii-id";
[all …]
H A Dtegra186-p2771-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra186-p3310.dtsi"
11 compatible = "nvidia,p2771-0000", "nvidia,tegra186";
23 #address-cells = <1>;
24 #size-cells = <0>;
30 remote-endpoint = <&xbar_i2s1_ep>;
38 dai-format = "i2s";
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/linux/drivers/phy/tegra/
H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
282 writel(value, priv->ao_regs + offset); in ao_writel()
287 return readl(priv->ao_regs + offset); in ao_readl()
296 /* USB 2.0 UTMI PHY support */
306 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
308 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
309 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
310 usb2->base.index = index; in tegra186_usb2_lane_probe()
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