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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DVOP2Instructions.td1 //===-- VOP2Instructions.td - Vector Instruction Definitions --------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 class VOP2e <bits<6> op, VOPProfile P> : Enc32 {
18 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
19 let Inst{16-9} = !if(P.HasSrc1, src1, 0);
20 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
21 let Inst{30-25} = op;
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H A DVOPCInstructions.td1 //===-- VOPCInstructions.td - Vector Instruction Definitions --------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
17 let Inst{8-0} = src0;
18 let Inst{16-9} = src1;
19 let Inst{24-17} = op;
20 let Inst{31-25} = 0x3e;
23 class VOPC_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> {
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H A DSIShrinkInstructions.cpp1 //===-- SIShrinkInstructions.cpp - Shrink Instructions --------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 /// The pass tries to use the 32-bit encoding for instructions when possible.
8 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "si-shrink-instructions"
21 "Number of 64-bit instruction reduced to 32-bit.");
23 "Number of literal constants folded into 32-bit instructions.");
86 /// This function checks \p MI for operands defined by a move immediate
88 /// can. This function assumes that \p MI is a VOP1, VOP2, or VOPC instructions.
91 assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI)); in foldImmediates()
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H A DSILowerControlFlow.cpp1 //===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 /// by writing to the 64-bit EXEC register (each bit corresponds to a
18 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
19 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
23 /// %vcc = V_CMP_GT_F32 %vgpr1, %vgpr2
24 /// %sgpr0 = SI_IF %vcc
32 /// %sgpr0 = S_AND_SAVEEXEC_B64 %vcc // Save and update the exec mask
48 /// %exec = S_OR_B64 %exec, %sgpr0 // Re-enable saved exec mask bits
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H A DSIOptimizeExecMaskingPreRA.cpp1 //===-- SIOptimizeExecMaskingPreRA.cpp ------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
24 #define DEBUG_TYPE "si-optimize-exec-masking-pre-ra"
55 return "SI optimize exec mask operations pre-RA"; in getPassName()
68 "SI optimize exec mask operations pre-RA", false, false)
71 "SI optimize exec mask operations pre-RA", false, false)
81 // See if there is a def between \p AndIdx and \p SelIdx that needs to live
82 // beyond \p AndIdx.
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H A DVOP3Instructions.td1 //===-- VOP3Instructions.td - Vector Instruction Definitions --------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // only VOP instruction that implicitly reads VCC.
43 class V_MUL_PROF<VOPProfile P> : VOP3_Profile<P> {
53 //===----------------------------------------------------------------------===//
55 //===----------------------------------------------------------------------===//
57 class VOP3Interp<string OpName, VOPProfile P, list<dag> pattern = []> :
58 VOP3_Pseudo<OpName, P, pattern> {
122 //===----------------------------------------------------------------------===//
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H A DSIWholeQuadMode.cpp1 //===-- SIWholeQuadMode.cpp - enter and suspend whole quad mode -----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// This pass adds instructions to enable whole quad mode (strict or non-strict)
16 /// non-strict WQM inactive lanes may control flow decisions.
37 /// S_OR_SAVEEXEC_B64 Tmp, -1
63 /// (2) when entire regions (e.g. if-else blocks or entire loops) only
64 /// consist of exact and don't-care instructions, the switch only has to
68 //===----------------------------------------------------------------------===//
87 #define DEBUG_TYPE "si-wqm"
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H A DAMDGPURegisterBankInfo.cpp1 //===- AMDGPURegisterBankInfo.cpp -------------------------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 /// VGPR (vector), and SGPR (scalar). Additionally the VCC register bank is a
17 /// sort of pseudo-register bank needed to represent SGPRs used in a vector
31 /// is naturally a bitmask with one bit per lane, in a 32 or 64-bit
32 /// register. These are represented with the VCC bank. During selection, we need
34 /// bank. To distinguish whether an SGPR should use the SGPR or VCC register
36 /// VCC bank value, otherwise it will be the SGPR bank. A scalar compare sets
37 /// SCC, which is a 1-bit unaddressable register. This will need to be copied to
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H A DSIInsertWaitcnts.cpp1 //===- SIInsertWaitcnts.cpp - Insert Wait Instructions --------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
17 /// finely-grained approach that keeps one timeline per event type could
20 /// the i-th-last LDS instruction, then an lgkmcnt(i) is actually sufficient,
24 //===----------------------------------------------------------------------===//
42 #define DEBUG_TYPE "si-insert-waitcnts"
44 DEBUG_COUNTER(ForceExpCounter, DEBUG_TYPE"-forceexp",
46 DEBUG_COUNTER(ForceLgkmCounter, DEBUG_TYPE"-forcelgkm",
48 DEBUG_COUNTER(ForceVMCounter, DEBUG_TYPE"-forcevm",
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H A DSIRegisterInfo.h1 //===-- SIRegisterInfo.h - SI Register Info Interface -------
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/freebsd/sys/contrib/device-tree/src/riscv/allwinner/
H A Dsun20i-d1-lichee-rv-86-panel-480p.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include "sun20i-d1-lichee-rv-86-panel.dtsi"
7 model = "Sipeed Lichee RV 86 Panel (480p)";
8 compatible = "sipeed,lichee-r
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/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun5i-r8-chip.dts5 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 * This file is dual-licensed: you can use it either under the terms
46 /dts-v1/;
47 #include "sun5i-r8.dtsi"
48 #include "sunxi-common-regulators.dtsi"
50 #include <dt-bindings/gpio/gpio.h>
51 #include <dt-bindings/interrupt-controller/irq.h>
54 model = "NextThing C.H.I.P.";
55 compatible = "nextthing,chip", "allwinner,sun5i-r8", "allwinner,sun5i-a13";
67 stdout-path = "serial0:115200n8";
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H A Dsun5i-gr8-chip-pro.dts5 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 * This file is dual-licensed: you can use it either under the terms
46 /dts-v1/;
47 #include "sun5i-gr8.dtsi"
48 #include "sunxi-common-regulators.dtsi"
50 #include <dt-bindings/gpio/gpio.h>
51 #include <dt-bindings/input/input.h>
52 #include <dt-bindings/interrupt-controller/irq.h>
55 model = "NextThing C.H.I.P. Pro";
56 compatible = "nextthing,chip-pro", "nextthing,gr8";
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/freebsd/crypto/openssh/
H A Dfreebsd-configure.sh5 --prefix=/usr
6 --sysconfdir=/etc/ssh
7 --with-pam
8 --with-ssl-dir=/usr
9 --without-tcp-wrappers
10 --with-libedit
11 --with-ssl-engine
12 --without-xauth
15 set -e
21 (cd $openssh && libtoolize --copy && autoheader && autoconf)
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/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dxlnx,zynqmp-ams.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/xlnx,zynqmp-am
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/freebsd/contrib/tcpdump/
H A Dprint-atm.c26 #include "netdissect-stdinc.h"
72 #define VCI_PPC 0x05 /* Point-to-point signal msg */
75 #define VCI_OAMF4EC 0x04 /* End-to-end OAM F4 flow cell */
130 #define OAM_FUNCTION_SPECIFIC_LEN 45 /* this excludes crc10 and cell-type/function-type */
144 { 0x4, "VCC OAM F5 flow segment" },
145 { 0x5, "VCC OAM F5 flow end-to-end" },
205 * Print an RFC 1483 LLC-encapsulated ATM frame.
209 const u_char *p, int length, int caplen) in atm_llc_print() argument
213 llc_hdrlen = llc_print(ndo, p, length, caplen, NULL, NULL); in atm_llc_print()
216 if (!ndo->ndo_suppress_default_print) in atm_llc_print()
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mq-librem5-devkit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 Purism SPC
6 /dts-v1/;
8 #include "dt-bindings/input/input.h"
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include "dt-binding
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/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dsh73a0-kzm9g.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the KZM-A9-GT board
7 * Based on sh73a0-kzm9g.dts
11 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
18 model = "KZM-A9-GT";
27 cpu0-supply = <&vdd_dvfs>;
28 operating-points = <1196000 1315000>, /* kHz uV */
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dallwinner,sun4i-a10-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Che
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/freebsd/usr.sbin/dumpcis/
H A Dcardinfo.h4 *-------------------------------------------------------------------------
6 /*-
7 * SPDX-License-Identifier: BSD-3-Clause
43 #define PIOCGSTATE _IOR('P', 1, struct slotstate) /* Get slot state */
44 #define PIOCGMEM _IOWR('P', 2, struct mem_desc) /* Get memory map */
45 #define PIOCSMEM _IOW('P', 3, struct mem_desc) /* Set memory map */
46 #define PIOCGIO _IOWR('P', 4, struct io_desc) /* Get I/O map */
47 #define PIOCSIO _IOW('P', 5, struct io_desc) /* Set I/O map */
48 #define PIOCSDRV _IOWR('P', 6, struct dev_desc) /* Set driver */
49 #define PIOCRWFLAG _IOW('P', 7, int) /* Set flags for drv use */
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dapq8096-db820c.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
6 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-binding
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H A Dapq8096-db820c.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
12 #include <dt-bindings/sound/qcom,q6afe.h>
13 #include <dt-bindings/sound/qcom,q6asm.h>
21 * P HSEC = Primary High Speed External Connector
27 * drawing no: LM25-P2751-1
38 * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
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H A Dsdm850-samsung-w737.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
11 #include <dt-bindings/input/gpio-keys.h>
12 #include <dt-binding
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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra186-p3310.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/mfd/max77620.h>
27 stdout-path = "serial0:115200n8";
38 phy-reset-gpios = <&gpio TEGRA186_MAIN_GPIO(M, 4)
40 phy-handle = <&phy>;
41 phy-mode = "rgmii";
44 #address-cells = <1>;
45 #size-cells = <0>;
47 phy: ethernet-phy@0 {
48 compatible = "ethernet-phy-ieee802.3-c22";
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8 //===----------------------------------------------------------------------===//
39 // non-pretty DWARF register names in assembly text. in printRegName()
53 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmOperand()
59 const MCOperand &Op = MI->getOperand(OpNo); in printU16ImmOperand()
61 Op.getExpr()->print(O, &MAI); in printU16ImmOperand()
65 // It's possible to end up with a 32-bit literal used with a 16-bit operand in printU16ImmOperand()
66 // with ignored high bits. Print as 32-bit anyway in that case. in printU16ImmOperand()
76 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmDecOperand()
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