Lines Matching +full:vcc +full:- +full:p
1 //===-- VOPCInstructions.td - Vector Instruction Definitions --------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
17 let Inst{8-0} = src0;
18 let Inst{16-9} = src1;
19 let Inst{24-17} = op;
20 let Inst{31-25} = 0x3e;
23 class VOPC_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> {
26 let Inst{8-0} = 0xf9; // sdwa
27 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
28 let Inst{24-17} = op;
29 let Inst{31-25} = 0x3e; // encoding
32 class VOPC_SDWA9e <bits<8> op, VOPProfile P> : VOP_SDWA9Be <P> {
35 let Inst{8-0} = 0xf9; // sdwa
36 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
37 let Inst{24-17} = op;
38 let Inst{31-25} = 0x3e; // encoding
39 let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
43 //===----------------------------------------------------------------------===//
45 //===----------------------------------------------------------------------===//
47 // VOPC instructions are a special case because for the 32-bit
48 // encoding, we want to display the implicit vcc write as if it were
74 // The destination for 32-bit encoding is implicit.
131 class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[],
133 InstSI<(outs), P.Ins32, "", pattern>,
142 string AsmOperands = P.Asm32;
149 let ReadsModeReg = P.Src0VT.isFP;
154 let Defs = !if(DefVcc, [VCC], []);
156 VOPProfile Pfl = P;
185 class VOPC_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
186 VOP_SDWA_Pseudo <OpName, P, pattern> {
193 VOPProfile p = ps.Pfl> :
200 !if (p.HasDst32,
201 !if (!eq(p.NumSrcArgs, 0),
203 (inst p.DstRC:$sdst),
204 !if (!eq(p.NumSrcArgs, 1),
206 (inst p.DstRC:$sdst, p.Src0RC32:$src0),
207 !if (!eq(p.NumSrcArgs, 2),
209 (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1),
210 // else - unreachable
213 !if (!eq(p.NumSrcArgs, 2),
215 (inst p.Src0RC32:$src0, p.Src1RC32:$src1),
216 !if (!eq(p.NumSrcArgs, 1),
218 (inst p.Src0RC32:$src1),
243 "vcc, "#!cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32,
255 class getVOPCPat64 <SDPatternOperator cond, VOPProfile P> : LetDummies {
256 list<dag> ret = !if(P.HasModifiers,
258 (setcc (P.Src0VT
259 !if(P.HasOMod,
260 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
261 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
262 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
264 [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]);
278 VOPC_Profile P,
283 def _e32 : VOPC_Pseudo <opName, P>,
287 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
288 let SchedRW = P.Schedule;
294 def _e64 : VOP3_Pseudo<opName, P, getVOPCPat64<cond, P>.ret>,
299 let SchedRW = P.Schedule;
304 if P.HasExtSDWA then
305 def _sdwa : VOPC_SDWA_Pseudo <opName, P> {
307 let SchedRW = P.Schedule;
313 if P.HasExtDPP then
314 def _e32_dpp : VOP_DPP_Pseudo<opName, P> {
315 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
316 let SchedRW = P.Schedule;
322 if P.HasExtVOP3DPP then
323 def _e64_dpp : VOP3_DPP_Pseudo<opName, P> {
325 let SchedRW = P.Schedule;
335 VOPC_Profile P, VOPC_Profile P_NoSDst,
338 VOPC_Pseudos <opName, P, cond, revOp, 1> {
375 if P.HasExtDPP then
384 if P.HasExtVOP3DPP then
476 //===----------------------------------------------------------------------===//
478 //===----------------------------------------------------------------------===//
766 //===----------------------------------------------------------------------===//
768 //===----------------------------------------------------------------------===//
788 let AsmSDWA = " vcc, $src0_modifiers, $src1_modifiers$clamp $src0_sel $src1_sel";
836 class getVOPCClassPat64 <VOPProfile P> {
840 (P.Src0VT (VOP3ModsNonCanonicalizing P.Src0VT:$src0, i32:$src0_modifiers)),
847 multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec,
849 def _e32 : VOPC_Pseudo <opName, p>,
851 let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]),
852 !if(DefVcc, [VCC], []));
853 let SchedRW = p.Schedule;
857 def _e64 : VOP3_Pseudo<opName, p, getVOPCClassPat64<p>.ret>,
860 let SchedRW = p.Schedule;
863 if p.HasExtSDWA then
864 def _sdwa : VOPC_SDWA_Pseudo <opName, p> {
865 let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]),
866 !if(DefVcc, [VCC], []));
867 let SchedRW = p.Schedule;
872 if p.HasExtDPP then
873 def _e32_dpp : VOP_DPP_Pseudo<opName, p> {
874 let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]),
875 !if(DefVcc, [VCC], []));
876 let SchedRW = p.Schedule;
881 if p.HasExtVOP3DPP then
882 def _e64_dpp : VOP3_DPP_Pseudo<opName, p> {
884 let SchedRW = p.Schedule;
892 VOPC_Profile P,
894 VOPC_Class_Pseudos <opName, P, 1, 1> {
920 if P.HasExtDPP then
928 if P.HasExtVOP3DPP then
988 //===----------------------------------------------------------------------===//
990 //===----------------------------------------------------------------------===//
993 // complaints it cannot replace i1 <-> i64/i32 if node was not morphed in place.
1158 //===----------------------------------------------------------------------===//
1160 //===----------------------------------------------------------------------===//
1166 let Inst{16-9} = src1;
1167 let Inst{24-17} = op;
1168 let Inst{31-25} = 0x3e;
1171 class VOPC_DPP_Base<bits<8> op, string OpName, VOPProfile P>
1172 : VOP_DPP_Base<OpName, P, P.InsDPP16, " " #P.AsmDPP16>,
1185 let Inst{8-0} = 0xfa;
1187 let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0);
1188 let Inst{48-40} = dpp_ctrl;
1191 let Inst{52} = !if (P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg
1192 let Inst{53} = !if (P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs
1193 let Inst{54} = !if (P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg
1194 let Inst{55} = !if (P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs
1195 let Inst{59-56} = bank_mask;
1196 let Inst{63-60} = row_mask;
1202 class VOPC_DPP8_Base<bits<8> op, string OpName, VOPProfile P>
1203 : VOP_DPP8_Base<OpName, P, P.InsDPP8, " " #P.AsmDPP8>,
1211 let Inst{8-0} = fi;
1213 let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0);
1214 let Inst{63-40} = dpp8{23-0};
1238 // Note ps is the non-dpp pseudo
1249 class VOPC64_DPP_Base<bits<10> op, string OpName, VOPProfile P>
1250 : VOP3_DPP_Base<OpName, P, 1>, VOP3_DPPe_Common<op, P> {
1260 let Inst{40-32} = 0xfa;
1261 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
1262 let Inst{80-72} = dpp_ctrl;
1265 // Inst{87-84} ignored by hw
1266 let Inst{91-88} = bank_mask;
1267 let Inst{95-92} = row_mask;
1286 let Inst{7-0} = sdst;
1292 let Inst{7-0} = ? ;
1295 class VOPC64_DPP8_Base<bits<10> op, string OpName, VOPProfile P>
1296 : VOP3_DPP8_Base<OpName, P>, VOP3_DPPe_Common<op, P> {
1303 let Inst{40-32} = fi;
1304 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
1305 let Inst{95-72} = dpp8{23-0};
1310 // Note ps is the non-dpp pseudo
1321 let Inst{7-0} = sdst;
1327 let Inst{7-0} = ? ;
1331 //===----------------------------------------------------------------------===//
1332 // Target-specific instruction encodings.
1333 //===----------------------------------------------------------------------===//
1335 //===----------------------------------------------------------------------===//
1337 //===----------------------------------------------------------------------===//
1344 VOPCe<op{7-0}>;
1350 let Inst{7-0} = sdst;
1358 def _e32_dpp#Gen.Suffix : VOPC_DPP16_SIMC<op{7-0}, psDPP, Gen.Subtarget>;
1359 def _e32_dpp_w32#Gen.Suffix : VOPC_DPP16<op{7-0}, psDPP> {
1364 def _e32_dpp_w64#Gen.Suffix : VOPC_DPP16<op{7-0}, psDPP> {
1365 let AsmString = psDPP.OpName # " vcc, " # AsmDPP;
1370 def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32>;
1371 def _e32_dpp8_w32#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32> {
1376 def _e32_dpp8_w64#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32> {
1377 let AsmString = ps32.OpName # " vcc, " # AsmDPP8;
1408 // the destination-less 32bit forms add it to the asmString here.
1410 VOPCe<op{7-0}>;
1417 let Inst{7-0} = sdst;
1425 def _e32_dpp#Gen.Suffix : VOPC_DPP16_SIMC<op{7-0}, psDPP,
1428 : VOPC_DPP16<op{7-0}, psDPP, asm_name> {
1434 : VOPC_DPP16<op{7-0}, psDPP, asm_name> {
1435 let AsmString = asm_name # " vcc, " # AsmDPP;
1440 def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32, asm_name>;
1442 : VOPC_DPP8<op{7-0}, ps32, asm_name> {
1448 : VOPC_DPP8<op{7-0}, ps32, asm_name> {
1449 let AsmString = asm_name # " vcc, " # AsmDPP8;
1475 VOPCe<op{7-0}> {
1482 let Inst{7-0} = ?; // sdst
1493 : VOPC_DPP16_SIMC<op{7-0}, psDPP, Gen.Subtarget> {
1497 def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32> {
1535 VOPCe<op{7-0}> {
1541 let Inst{7-0} = ? ; // sdst
1549 def _e32_dpp#Gen.Suffix : VOPC_DPP16_SIMC<op{7-0}, psDPP,
1551 def _e32_dpp8#Gen.Suffix : VOPC_DPP8<op{7-0}, ps32, asm_name>;
1792 //===----------------------------------------------------------------------===//
1794 //===----------------------------------------------------------------------===//
1800 VOPCe<op{7-0}>;
1807 let Inst{7-0} = sdst;
1813 VOPC_SDWA9e<op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1821 VOPCe<op{7-0}> {
1829 let Inst{7-0} = ?; // sdst
1837 VOPC_SDWA9e<op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").Pfl> {
1905 //===----------------------------------------------------------------------===//
1907 //===----------------------------------------------------------------------===//
1913 VOPCe<op{7-0}>;
1920 let Inst{7-0} = sdst;
2142 //===----------------------------------------------------------------------===//
2144 //===----------------------------------------------------------------------===//
2150 VOPCe<op{7-0}>;
2158 let Inst{7-0} = sdst;
2165 VOPC_SDWAe <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
2170 VOPC_SDWA9e <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;