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/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da8xx_enums.xml10 <value value="0" name="A8XX_TP0_NCTX_REG"/>
11 <value value="1" name="A8XX_TP0_CTX0_3D_CVS_REG"/>
12 <value value="2" name="A8XX_TP0_CTX0_3D_CPS_REG"/>
13 <value value="3" name="A8XX_TP0_CTX1_3D_CVS_REG"/>
14 <value value="4" name="A8XX_TP0_CTX1_3D_CPS_REG"/>
15 <value value="5" name="A8XX_TP0_CTX2_3D_CPS_REG"/>
16 <value value="6" name="A8XX_TP0_CTX3_3D_CPS_REG"/>
17 <value value="9" name="A8XX_TP0_TMO_DATA"/>
18 <value value="10" name="A8XX_TP0_SMO_DATA"/>
19 <value value="11" name="A8XX_TP0_MIPMAP_BASE_DATA"/>
[all …]
H A Da7xx_enums.xml10 <value value="0" name="A7XX_TP0_NCTX_REG"/>
11 <value value="1" name="A7XX_TP0_CTX0_3D_CVS_REG"/>
12 <value value="2" name="A7XX_TP0_CTX0_3D_CPS_REG"/>
13 <value value="3" name="A7XX_TP0_CTX1_3D_CVS_REG"/>
14 <value value="4" name="A7XX_TP0_CTX1_3D_CPS_REG"/>
15 <value value="5" name="A7XX_TP0_CTX2_3D_CPS_REG"/>
16 <value value="6" name="A7XX_TP0_CTX3_3D_CPS_REG"/>
17 <value value="9" name="A7XX_TP0_TMO_DATA"/>
18 <value value="10" name="A7XX_TP0_SMO_DATA"/>
19 <value value="11" name="A7XX_TP0_MIPMAP_BASE_DATA"/>
[all …]
H A Da2xx.xml11 <value name="DITHER_PIXEL" value="0"/>
12 <value name="DITHER_SUBPIXEL" value="1"/>
16 <value name="COLORX_4_4_4_4" value="0"/>
17 <value name="COLORX_1_5_5_5" value="1"/>
18 <value name="COLORX_5_6_5" value="2"/>
19 <value name="COLORX_8" value="3"/>
20 <value name="COLORX_8_8" value="4"/>
21 <value name="COLORX_8_8_8_8" value="5"/>
22 <value name="COLORX_S8_8_8_8" value="6"/>
23 <value name="COLORX_16_FLOAT" value="7"/>
[all …]
H A Da4xx.xml10 <value name="RB4_A8_UNORM" value="0x01"/>
11 <value name="RB4_R8_UNORM" value="0x02"/>
12 <value name="RB4_R8_SNORM" value="0x03"/>
13 <value name="RB4_R8_UINT" value="0x04"/>
14 <value name="RB4_R8_SINT" value="0x05"/>
16 <value name="RB4_R4G4B4A4_UNORM" value="0x08"/>
17 <value name="RB4_R5G5B5A1_UNORM" value="0x0a"/>
18 <value name="RB4_R5G6B5_UNORM" value="0x0e"/>
19 <value name="RB4_R8G8_UNORM" value="0x0f"/>
20 <value name="RB4_R8G8_SNORM" value="0x10"/>
[all …]
H A Da3xx.xml10 <value name="LINEAR" value="0"/>
11 <value name="TILE_4X4" value="1"/> <!-- "normal" case for textures -->
12 <value name="TILE_32X32" value="2"/> <!-- only used in GMEM -->
13 <value name="TILE_4X2" value="3"/> <!-- only used for CrCb -->
17 <value name="HLSQ_BLOCK_ID_TP_TEX" value="2"/>
18 <value name="HLSQ_BLOCK_ID_TP_MIPMAP" value="3"/>
19 <value name="HLSQ_BLOCK_ID_SP_VS" value="4"/>
20 <value name="HLSQ_BLOCK_ID_SP_FS" value="6"/>
24 <value name="INVALIDATE" value="1"/>
28 <value name="VFMT_32_FLOAT" value="0x0"/>
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Dfw.h400 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ argument
401 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))
402 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ argument
403 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
404 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ argument
405 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16))
406 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ argument
407 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0))
416 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ argument
417 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))
[all …]
/linux/tools/testing/selftests/kvm/include/x86/
H A Devmcs.h268 static inline int evmcs_vmptrst(u64 *value) in evmcs_vmptrst() argument
270 *value = current_vp_assist->current_nested_vmcs & in evmcs_vmptrst()
276 static inline int evmcs_vmread(u64 encoding, u64 *value) in evmcs_vmread() argument
280 *value = current_evmcs->guest_rip; in evmcs_vmread()
283 *value = current_evmcs->guest_rsp; in evmcs_vmread()
286 *value = current_evmcs->guest_rflags; in evmcs_vmread()
289 *value = current_evmcs->host_ia32_pat; in evmcs_vmread()
292 *value = current_evmcs->host_ia32_efer; in evmcs_vmread()
295 *value = current_evmcs->host_cr0; in evmcs_vmread()
298 *value in evmcs_vmread()
675 evmcs_vmwrite(u64 encoding,u64 value) evmcs_vmwrite() argument
[all...]
/linux/drivers/gpu/drm/msm/registers/display/
H A Dmdp_common.xml11 <value name="CHROMA_FULL" value="0"/>
12 <value name="CHROMA_H2V1" value="1"/>
13 <value name="CHROMA_H1V2" value="2"/>
14 <value name="CHROMA_420" value="3"/>
18 <value name="MDP_PLANE_INTERLEAVED" value="0"/>
19 <value name="MDP_PLANE_PLANAR" value="1"/>
20 <value name="MDP_PLANE_PSEUDO_PLANAR" value="2"/>
24 <value name="STAGE_UNUSED" value="0"/>
25 <value name="STAGE_BASE" value="1"/>
26 <value name="STAGE0" value="2"/> <!-- zorder 0 -->
[all …]
/linux/drivers/phy/tegra/
H A Dxusb-tegra210.c468 u32 value; in tegra210_pex_uphy_enable() local
486 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
487 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_pex_uphy_enable()
489 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_pex_uphy_enable()
491 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
493 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
494 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_pex_uphy_enable()
496 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_pex_uphy_enable()
498 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
500 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
[all …]
H A Dxusb-tegra124.c227 u32 value; in tegra124_xusb_padctl_enable() local
234 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
235 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; in tegra124_xusb_padctl_enable()
236 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
240 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
241 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra124_xusb_padctl_enable()
242 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
246 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
247 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; in tegra124_xusb_padctl_enable()
248 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
[all …]
H A Dxusb-tegra186.c281 static inline void ao_writel(struct tegra186_xusb_padctl *priv, u32 value, unsigned int offset) in ao_writel() argument
283 writel(value, priv->ao_regs + offset); in ao_writel()
337 u32 value; in tegra186_utmi_enable_phy_sleepwalk() local
342 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
343 value &= ~MASTER_ENABLE; in tegra186_utmi_enable_phy_sleepwalk()
344 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
347 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
348 value |= MASTER_CFG_SEL; in tegra186_utmi_enable_phy_sleepwalk()
349 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
352 value = ao_readl(priv, XUSB_AO_USB_DEBOUNCE_DEL); in tegra186_utmi_enable_phy_sleepwalk()
[all …]
/linux/drivers/video/fbdev/riva/
H A Dnvreg.h34 #define SetBF(mask,value) ((value) << (0?mask)) argument
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ argument
38 | SetBF(mask,value)))
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
51 #define DEVICE_DEF(device,mask,value) \ argument
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) argument
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
59 #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) argument
60 #define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) argument
[all …]
/linux/tools/power/x86/intel-speed-select/
H A Disst-display.c85 char *value) in format_and_print_txt() argument
102 if (header && value) { in format_and_print_txt()
104 fprintf(outf, "%s:%s\n", header, value); in format_and_print_txt()
112 static void format_and_print(FILE *outf, int level, char *header, char *value) in format_and_print() argument
119 format_and_print_txt(outf, level, header, value); in format_and_print()
139 if (value) { in format_and_print()
144 fprintf(outf, "\"%s\"", value); in format_and_print()
222 static char value[1024]; in _isst_pbf_display_information() local
228 snprintf(value, sizeof(value), "%d", in _isst_pbf_display_information()
230 format_and_print(outf, disp_level + 1, header, value); in _isst_pbf_display_information()
[all …]
/linux/drivers/media/pci/cx25821/
H A Dcx25821-medusa-video.c24 u32 value = 0; in medusa_enable_bluefield_output() local
63 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); in medusa_enable_bluefield_output()
64 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
66 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
67 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); in medusa_enable_bluefield_output()
69 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); in medusa_enable_bluefield_output()
70 value &= 0xFFFFFF7F; in medusa_enable_bluefield_output()
72 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
73 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); in medusa_enable_bluefield_output()
80 u32 value = 0; in medusa_initialize_ntsc() local
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h57 * bit will be set. Otherwise the value of the register before
62 int64_t value:63; member
67 * bit will be set. Otherwise the value of the register before
72 int32_t value:31; member
77 * bit will be set. Otherwise the value of the register before
82 int16_t value:15; member
87 * bit will be set. Otherwise the value of the register before
92 int8_t value:7; member
97 * the error bit will be set. Otherwise the value of the
121 * @noadd: 0 = Store value is atomically added to the current value
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac4_core.c46 u32 value; in dwmac4_core_init() local
48 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_core_init()
49 writel(value | GMAC_CORE_INIT, ioaddr + GMAC_CONFIG); in dwmac4_core_init()
67 u32 value; in dwmac4_irq_modify() local
70 value = readl(int_mask) & ~disable; in dwmac4_irq_modify()
71 value |= enable; in dwmac4_irq_modify()
72 writel(value, int_mask); in dwmac4_irq_modify()
88 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0); in dwmac4_rx_queue_enable() local
90 value &= GMAC_RX_QUEUE_CLEAR(queue); in dwmac4_rx_queue_enable()
92 value |= GMAC_RX_AV_QUEUE_ENABLE(queue); in dwmac4_rx_queue_enable()
[all …]
H A Dstmmac_vlan.c168 u32 value; in vlan_update_hash() local
172 value = readl(ioaddr + VLAN_TAG); in vlan_update_hash()
175 value |= VLAN_VTHM | VLAN_ETV; in vlan_update_hash()
177 value |= VLAN_ESVL; in vlan_update_hash()
178 value |= VLAN_DOVLTC; in vlan_update_hash()
180 value &= ~VLAN_ESVL; in vlan_update_hash()
181 value &= ~VLAN_DOVLTC; in vlan_update_hash()
184 writel(value, ioaddr + VLAN_TAG); in vlan_update_hash()
186 value &= ~(VLAN_VTHM | VLAN_ETV | VLAN_ESVL); in vlan_update_hash()
187 value in vlan_update_hash()
188 u32 value = VLAN_ETV; vlan_update_hash() local
214 u32 value; vlan_enable() local
237 u32 value = readl(ioaddr + VLAN_TAG); vlan_set_hw_mode() local
261 u32 value = readl(ioaddr + XGMAC_PACKET_FILTER); dwxgmac2_update_vlan_hash() local
283 u32 value = readl(ioaddr + XGMAC_PACKET_FILTER); dwxgmac2_update_vlan_hash() local
306 u32 value = readl(ioaddr + XGMAC_PACKET_FILTER); dwxgmac2_update_vlan_hash() local
[all...]
H A Ddwxgmac2_dma.c13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset() local
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, in dwxgmac2_dma_reset()
19 !(value & XGMAC_SWR), 0, 100000); in dwxgmac2_dma_reset()
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init() local
28 value |= XGMAC_AAL; in dwxgmac2_dma_init()
31 value |= XGMAC_EAME; in dwxgmac2_dma_init()
33 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
39 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_init()
40 value = u32_replace_bits(value, XGMAC_INTM_MODE1, in dwxgmac2_dma_init()
[all …]
/linux/drivers/net/wwan/t7xx/
H A Dt7xx_dpmaif.c37 u32 value, ul_intr_enable, dl_intr_enable; in t7xx_dpmaif_init_intr() local
50 value, (value & ul_intr_enable) != ul_intr_enable, 0, in t7xx_dpmaif_init_intr()
65 value, (value & ul_intr_enable) != ul_intr_enable, 0, in t7xx_dpmaif_init_intr()
74 value = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0); in t7xx_dpmaif_init_intr()
75 value |= DPMAIF_DL_INT_Q2APTOP | DPMAIF_DL_INT_Q2TOQ1; in t7xx_dpmaif_init_intr()
76 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0); in t7xx_dpmaif_init_intr()
85 u32 value, ul_int_que_done; in t7xx_dpmaif_mask_ulq_intr() local
94 value, (value & ul_int_que_done) == ul_int_que_done, 0, in t7xx_dpmaif_mask_ulq_intr()
99 value); in t7xx_dpmaif_mask_ulq_intr()
105 u32 value, ul_int_que_done; in t7xx_dpmaif_unmask_ulq_intr() local
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dsil-sii8620.h15 /* Vendor ID Low byte, default value: 0x01 */
18 /* Vendor ID High byte, default value: 0x00 */
21 /* Device ID Low byte, default value: 0x60 */
24 /* Device ID High byte, default value: 0x86 */
27 /* Device Revision, default value: 0x10 */
30 /* OTP DBYTE510, default value: 0x00 */
33 /* System Control #1, default value: 0x00 */
44 /* System Control DPD, default value: 0x90 */
54 /* Dual link Control, default value: 0x00 */
65 /* PWD Software Reset, default value: 0x20 */
[all …]
/linux/fs/nfsd/
H A Dnfs4xdr_gen.c740 xdrgen_encode_int32_t(struct xdr_stream *xdr, const int32_t value) in xdrgen_encode_int32_t() argument
742 return xdrgen_encode_int(xdr, value); in xdrgen_encode_int32_t()
746 xdrgen_encode_uint32_t(struct xdr_stream *xdr, const uint32_t value) in xdrgen_encode_uint32_t() argument
748 return xdrgen_encode_unsigned_int(xdr, value); in xdrgen_encode_uint32_t()
752 xdrgen_encode_int64_t(struct xdr_stream *xdr, const int64_t value) in xdrgen_encode_int64_t() argument
754 return xdrgen_encode_hyper(xdr, value); in xdrgen_encode_int64_t()
758 xdrgen_encode_uint64_t(struct xdr_stream *xdr, const uint64_t value) in xdrgen_encode_uint64_t() argument
760 return xdrgen_encode_unsigned_hyper(xdr, value); in xdrgen_encode_uint64_t()
764 xdrgen_encode_nfsstat4(struct xdr_stream *xdr, nfsstat4 value) in xdrgen_encode_nfsstat4() argument
766 return xdr_stream_encode_u32(xdr, value) == XDR_UNIT; in xdrgen_encode_nfsstat4()
[all …]
/linux/tools/perf/util/annotate-arch/
H A Dannotate-powerpc.c146 int value; member
164 * value => 21
168 { .name = "OP_31_XOP_LXSIWZX", .value = 12, },
169 { .name = "OP_31_XOP_LWARX", .value = 20, },
170 { .name = "OP_31_XOP_LDX", .value = 21, },
171 { .name = "OP_31_XOP_LWZX", .value = 23, },
172 { .name = "OP_31_XOP_LDUX", .value = 53, },
173 { .name = "OP_31_XOP_LWZUX", .value = 55, },
174 { .name = "OP_31_XOP_LXSIWAX", .value = 76, },
175 { .name = "OP_31_XOP_LDARX", .value = 84, },
[all …]
/linux/tools/testing/selftests/bpf/test_kmods/
H A Dbpf_testmod.h28 /* BPF iter that returns *value* *n* times in a row */
30 s64 value; member
60 int (*tramp_1)(int value);
61 int (*tramp_2)(int value);
62 int (*tramp_3)(int value);
63 int (*tramp_4)(int value);
64 int (*tramp_5)(int value);
65 int (*tramp_6)(int value);
66 int (*tramp_7)(int value);
67 int (*tramp_8)(int value);
[all …]
/linux/lib/crc/mips/
H A Dcrc32.h31 #define __CRC32(crc, value, op, SZ, TYPE) \ argument
40 : "r" (value)); \
43 #define _CRC32_crc32b(crc, value) __CRC32(crc, value, crc32b, 0, 0) argument
44 #define _CRC32_crc32h(crc, value) __CRC32(crc, value, crc32h, 1, 0) argument
45 #define _CRC32_crc32w(crc, value) __CRC32(crc, value, crc32w, 2, 0) argument
46 #define _CRC32_crc32d(crc, value) __CRC32(crc, value, crc32d, 3, 0) argument
47 #define _CRC32_crc32cb(crc, value) __CRC32(crc, value, crc32cb, 0, 1) argument
48 #define _CRC32_crc32ch(crc, value) __CRC32(crc, value, crc32ch, 1, 1) argument
49 #define _CRC32_crc32cw(crc, value) __CRC32(crc, value, crc32cw, 2, 1) argument
50 #define _CRC32_crc32cd(crc, value) __CRC32(crc, value, crc32cd, 3, 1) argument
[all …]
/linux/drivers/gpu/drm/tegra/
H A Dsor.c492 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl() local
494 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
496 return value; in tegra_sor_readl()
499 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
502 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
503 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
550 u32 value; in tegra_clk_sor_pad_set_parent() local
552 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
553 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_clk_sor_pad_set_parent()
557 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_clk_sor_pad_set_parent()
[all …]

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