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/linux/drivers/irqchip/
H A Dirq-gic-v2m.c3 * ARM GIC v2m MSI(-X) support
58 /* List of flags for specific v2m implementation */
74 u32 flags; /* v2m flags for specific implementation */
77 static phys_addr_t gicv2m_get_msi_addr(struct v2m_data *v2m, int hwirq) in gicv2m_get_msi_addr() argument
79 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) in gicv2m_get_msi_addr()
80 return v2m->res.start | ((hwirq - 32) << 3); in gicv2m_get_msi_addr()
82 return v2m->res.start + V2M_MSI_SETSPI_NS; in gicv2m_get_msi_addr()
87 struct v2m_data *v2m = irq_data_get_irq_chip_data(data); in gicv2m_compose_msi_msg() local
88 phys_addr_t addr = gicv2m_get_msi_addr(v2m, data->hwirq); in gicv2m_compose_msi_msg()
93 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) in gicv2m_compose_msi_msg()
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2m.dtsi6 * V2M-P1
14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m-rs1.dtsi!
79 compatible = "arm,vexpress,v2m-p1", "simple-bus";
366 clock-output-names = "v2m:clk24mhz";
373 clock-output-names = "v2m:refclk1mhz";
380 clock-output-names = "v2m:refclk32khz";
387 label = "v2m:green:user1";
393 label = "v2m:green:user2";
399 label = "v2m:green:user3";
[all …]
H A Dvexpress-v2m-rs1.dtsi6 * V2M-P1
14 * original variant (vexpress-v2m.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m.dtsi!
35 clock-output-names = "v2m:clk24mhz";
42 clock-output-names = "v2m:refclk1mhz";
49 clock-output-names = "v2m:refclk32khz";
56 label = "v2m:green:user1";
62 label = "v2m:green:user2";
68 label = "v2m:green:user3";
74 label = "v2m:green:user4";
[all …]
/linux/Documentation/devicetree/bindings/soc/renesas/
H A Drenesas,rzv2m-pwc.yaml7 title: Renesas RZ/V2M External Power Sequence Controller (PWC)
10 The PWC IP found in the RZ/V2M family of chips comes with the below
24 - renesas,r9a09g011-pwc # RZ/V2M
H A Drenesas,r9a09g011-sys.yaml7 title: Renesas RZ/V2M System Configuration (SYS)
13 The RZ/V2M-alike SYS (System Configuration) controls the overall
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap80x.dtsi95 gic_v2m0: v2m@280000 {
96 compatible = "arm,gic-v2m-frame";
102 gic_v2m1: v2m@290000 {
103 compatible = "arm,gic-v2m-frame";
109 gic_v2m2: v2m@2a0000 {
110 compatible = "arm,gic-v2m-frame";
116 gic_v2m3: v2m@2b0000 {
117 compatible = "arm,gic-v2m-frame";
/linux/Documentation/devicetree/bindings/arm/
H A Darm,vexpress-juno.yaml83 V2M-Juno) was introduced as a vehicle for evaluating big.LITTLE on
91 (V2M-Juno r1) was introduced mainly aimed at development of PCIe
100 (V2M-Juno r2). It has the same feature set as Juno r0 and r1. See
154 - arm,vexpress,v2m-p1
178 - arm,vexpress,v2m-p1
181 arm,v2m-memory-map:
/linux/arch/arm64/boot/dts/arm/
H A Drtsm_ve-motherboard.dtsi15 clock-output-names = "v2m:clk24mhz";
22 clock-output-names = "v2m:refclk1mhz";
29 clock-output-names = "v2m:refclk32khz";
50 clock-output-names = "v2m:oscclk1";
86 compatible = "arm,vexpress,v2m-p1", "simple-bus";
H A Drtsm_ve-motherboard-rs2.dtsi5 * "rs2" extension for the v2m motherboard
10 arm,v2m-memory-map = "rs2";
H A Dfoundation-v8.dtsi108 clock-output-names = "v2m:clk24mhz";
115 clock-output-names = "v2m:refclk1mhz";
122 clock-output-names = "v2m:refclk32khz";
126 compatible = "arm,vexpress,v2m-p1", "simple-bus";
H A Djuno-base.dtsi83 v2m_0: v2m@0 {
84 compatible = "arm,gic-v2m-frame";
89 v2m@10000 {
90 compatible = "arm,gic-v2m-frame";
95 v2m@20000 {
96 compatible = "arm,gic-v2m-frame";
101 v2m@30000 {
102 compatible = "arm,gic-v2m-frame";
/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,rzg2l-cpg.yaml7 title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
14 Standby Mode share the same register block. On RZ/V2M, the functionality is
31 - renesas,r9a09g011-cpg # RZ/V2M
/linux/arch/arm/mach-versatile/
H A DMakefile18 obj-$(CONFIG_ARCH_VEXPRESS) := v2m.o
26 obj-$(CONFIG_ARCH_MPS2) += v2m-mps2.o
/linux/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,rzv2m-pinctrl.yaml7 title: Renesas RZ/V2M combined Pin and GPIO controller
14 The Renesas RZ/V2M SoC features a combined Pin and GPIO controller.
22 const: renesas,r9a09g011-pinctrl # RZ/V2M
/linux/Documentation/devicetree/bindings/i2c/
H A Drenesas,rzv2m.yaml7 title: Renesas RZ/V2M I2C Bus Interface
19 - renesas,r9a09g011-i2c # RZ/V2M
/linux/Documentation/devicetree/bindings/usb/
H A Drenesas,usb-xhci.yaml39 - renesas,r9a09g011-xhci # RZ/V2M
41 - const: renesas,rzv2m-xhci # RZ/{V2M, V2MA}
H A Drenesas,rzv2m-usb3drd.yaml7 title: Renesas RZ/V2M USB 3.1 DRD controller
21 - renesas,r9a09g011-usb3drd # RZ/V2M
/linux/Documentation/devicetree/bindings/watchdog/
H A Drenesas,wdt.yaml37 - renesas,r9a09g011-wdt # RZ/V2M
38 - const: renesas,rzv2m-wdt # RZ/V2M
/linux/include/dt-bindings/pinctrl/
H A Drzv2m-pinctrl.h3 * This header provides constants for Renesas RZ/V2M pinctrl bindings.
/linux/drivers/usb/host/
H A Dxhci-rzv2m.c3 * xHCI host controller driver for RZ/V2M
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g011-v2mevk2.dts3 * Device Tree Source for the RZ/V2M (r9a09g011) Evaluation Kit Board
14 model = "RZ/V2M Evaluation Kit 2.0";
/linux/Documentation/devicetree/bindings/serial/
H A Drenesas,em-uart.yaml17 - renesas,r9a09g011-uart # RZ/V2M
/linux/Documentation/hwmon/
H A Dvexpress.rst17 * Section "4.4.14. System Configuration registers" of the V2M-P1 TRM:
/linux/Documentation/devicetree/bindings/spi/
H A Drenesas,rzv2m-csi.yaml7 title: Renesas RZ/V2M Clocked Serial Interface (CSI)
/linux/Documentation/devicetree/bindings/net/
H A Drenesas,etheravb.yaml54 - renesas,etheravb-r9a09g011 # RZ/V2M
55 - const: renesas,etheravb-rzv2m # RZ/V2M compatible

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