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Searched full:usxgmii (Results 1 – 18 of 18) sorted by relevance

/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-qds-13bb.dtso28 phy-mode = "usxgmii";
63 phy-mode = "usxgmii";
70 phy-mode = "usxgmii";
77 phy-mode = "usxgmii";
84 phy-mode = "usxgmii";
H A Dfsl-lx2160a-bluebox3.dts58 phy-mode = "usxgmii";
64 phy-mode = "usxgmii";
70 phy-mode = "usxgmii";
76 phy-mode = "usxgmii";
H A Dfsl-lx2160a-rdb.dts42 phy-connection-type = "usxgmii";
48 phy-connection-type = "usxgmii";
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-evm-usxgmii-exp1-exp2.dtso3 * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1
31 phy-mode = "usxgmii";
43 phy-mode = "usxgmii";
55 assigned-clock-parents = <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */
/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,mt7988-xfi-tphy.yaml14 used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
39 mediatek,usxgmii-performance-errata:
75 mediatek,usxgmii-performance-errata;
H A Dtransmit-amplitude.yaml48 - usxgmii
/linux/drivers/clk/mediatek/
H A Dclk-mt7988-xfipll.c15 /* Register to control USXGMII XFI PLL analog */
58 /* Apply software workaround for USXGMII PLL TCL issue */ in clk_mt7988_xfipll_probe()
/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml84 - usxgmii
149 phy-mode = "usxgmii";
/linux/drivers/phy/mediatek/
H A DKconfig25 via the USXGMII PCS found in MediaTek SoCs with 10G Ethernet.
/linux/Documentation/devicetree/bindings/net/pcs/
H A Dsnps,dw-xpcs.yaml15 the Media Independent Interface (XGMII, USXGMII, XLGMII, GMII, etc)
/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddpmac.h50 * @DPMAC_ETH_IF_USXGMII: USXGMII interface
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmscc,ocelot.yaml53 - phy-mode = "usxgmii": on ports 0, 1, 2, 3
/linux/drivers/phy/cadence/
H A Dphy-cadence-torrent.c710 return "USXGMII"; in cdns_torrent_get_phy_type()
2341 * for SGMII/QSGMII/USXGMII in cdns_torrent_phy_init()
3417 /* USXGMII and SGMII/QSGMII link configuration */
3451 /* Multilink USXGMII, using PLL0, 156.25 MHz Ref clk, no SSC */
3484 /* TI J7200, Multilink USXGMII, using PLL0, 156.25 MHz Ref clk, no SSC */
3533 /* PCIe and USXGMII link configuration */
3569 * Multilink USXGMII, using PLL1, 156.25 MHz Ref clk, no SSC
3627 /* TI USXGMII configuration: Enable cmn_refclk_rcv_out_en */
3637 /* Single USXGMII link configuration */
3659 /* Single link USXGMII, 156.25 MHz Ref clk, no SSC */
/linux/drivers/net/phy/
H A Dphylink.c2052 * For some interface modes (e.g. RXAUI, XAUI and USXGMII) switching in phylink_validate_phy()
3965 * phylink_decode_usxgmii_word() - decode the USXGMII word from a MAC PCS
3967 * @lpa: a 16 bit value which stores the USXGMII auto-negotiation word
3969 * Helper for MAC PCS supporting the USXGMII protocol and the auto-negotiation
3970 * code word. Decode the USXGMII code word and populate the corresponding fields
4015 * word is the same as the USXGMII word, except it only supports speeds up to
H A Dmxl-gpy.c540 /* Interface mode is fixed for USXGMII and integrated PHY */ in gpy_update_interface()
/linux/drivers/net/dsa/mv88e6xxx/
H A Dpcs-639x.c909 "can't read USXGMII status: %pe\n", ERR_PTR(err)); in mv88e6393x_xg_pcs_get_state()
/linux/drivers/net/pcs/
H A Dpcs-xpcs.c368 /* By default, in USXGMII mode XPCS operates at 10G baud and in _xpcs_config_aneg_c73()
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dcgx.c58 [LMAC_MODE_USXGMII] = "USXGMII",