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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-qds-13bb.dtso28 phy-mode = "usxgmii";
63 phy-mode = "usxgmii";
70 phy-mode = "usxgmii";
77 phy-mode = "usxgmii";
84 phy-mode = "usxgmii";
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-evm-usxgmii-exp1-exp2.dtso3 * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1
31 phy-mode = "usxgmii";
43 phy-mode = "usxgmii";
55 assigned-clock-parents = <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */
/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,mt7988-xfi-tphy.yaml14 used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
39 mediatek,usxgmii-performance-errata:
75 mediatek,usxgmii-performance-errata;
/linux/drivers/clk/mediatek/
H A Dclk-mt7988-xfipll.c15 /* Register to control USXGMII XFI PLL analog */
58 /* Apply software workaround for USXGMII PLL TCL issue */ in clk_mt7988_xfipll_probe()
/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml84 - usxgmii
149 phy-mode = "usxgmii";
H A Dqcom,ipq9574-ppe.yaml28 supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There
495 phy-mode = "usxgmii";
515 phy-mode = "usxgmii";
/linux/drivers/net/pcs/
H A Dpcs-lynx.c166 /* Configure device ability for the USXGMII Replicator */ in lynx_pcs_config_usxgmii()
259 /* At the moment, only in-band AN is supported for USXGMII in lynx_pcs_link_up()
H A Dpcs-xpcs.c412 /* By default, in USXGMII mode XPCS operates at 10G baud and in _xpcs_config_aneg_c73()
/linux/drivers/phy/mediatek/
H A DKconfig25 via the USXGMII PCS found in MediaTek SoCs with 10G Ethernet.
/linux/include/uapi/linux/
H A Dmdio.h501 /* UsxgmiiChannelInfo[15:0] for USXGMII in-band auto-negotiation.*/
504 #define MDIO_USXGMII_SPD_MASK 0x0e00 /* USXGMII speed mask */
505 #define MDIO_USXGMII_FULL_DUPLEX 0x1000 /* USXGMII full duplex */
506 #define MDIO_USXGMII_DPX_SPD_MASK 0x1e00 /* USXGMII duplex and speed bits */
/linux/Documentation/devicetree/bindings/net/pcs/
H A Dsnps,dw-xpcs.yaml15 the Media Independent Interface (XGMII, USXGMII, XLGMII, GMII, etc)
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmscc,ocelot.yaml53 - phy-mode = "usxgmii": on ports 0, 1, 2, 3
/linux/drivers/net/phy/
H A Dphylink.c2070 * For some interface modes (e.g. RXAUI, XAUI and USXGMII) switching in phylink_validate_phy()
4060 * phylink_decode_usxgmii_word() - decode the USXGMII word from a MAC PCS
4062 * @lpa: a 16 bit value which stores the USXGMII auto-negotiation word
4064 * Helper for MAC PCS supporting the USXGMII protocol and the auto-negotiation
4065 * code word. Decode the USXGMII code word and populate the corresponding fields
4110 * word is the same as the USXGMII word, except it only supports speeds up to
/linux/drivers/net/dsa/mv88e6xxx/
H A Dpcs-639x.c909 "can't read USXGMII status: %pe\n", ERR_PTR(err)); in mv88e6393x_xg_pcs_get_state()
/linux/include/linux/
H A Dphy.h105 * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII
272 return "usxgmii"; in phy_modes()
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dcgx.c58 [LMAC_MODE_USXGMII] = "USXGMII",