Home
last modified time | relevance | path

Searched +full:use +full:- +full:internal +full:- +full:divider (Results 1 – 25 of 122) sorted by relevance

12345

/linux/Documentation/devicetree/bindings/iio/adc/
H A Dingenic,adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2019-2020 Artur Rojek
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Artur Rojek <contact@artur-rojek.eu>
17 ADC clients must use the format described in
18 https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml,
19 giving a phandle and IIO specifier pair ("io-channels") to the ADC controller.
24 - ingenic,jz4725b-adc
25 - ingenic,jz4740-adc
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5351.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
12 output clocks are accessible. The internal structure of the clock generators
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
24 - silabs,si5351a # Si5351A, 20-QFN package
25 - silabs,si5351a-msop # Si5351A, 10-MSOP package
26 - silabs,si5351b # Si5351B, 20-QFN package
[all …]
H A Dsilabs,si5341.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mike Looijmans <mike.looijmans@topic.nl>
18 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
20 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
22 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
26 in turn can be directed to any of the 10 (or 4) outputs through a divider.
27 The internal structure of the clock generators can be found in [2].
33 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
[all …]
H A Dstericsson,u8500-clks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 (U8500) clocks
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Linus Walleij <linus.walleij@linaro.org>
14 DB8500 digital baseband system-on-chip and its siblings such as
16 itself, not off-chip clocks. There are four different on-chip
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
[all …]
/linux/Documentation/hwmon/
H A Dpc87360.rst22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
58 PC87364 - 3 3 - 0xE4
60 PC87366 11 3 3 3-4 0xE9
[all …]
H A Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
66 Sensor Voltage Mode Temp Mode Default Use (from the datasheet)
69 Reading 3 temp2 Internal thermal diode
[all …]
/linux/drivers/hwmon/
H A Dmlxreg-fan.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
27 * FAN datasheet defines the formula for RPM calculations as RPM = 15/t-high.
28 * The logic in a programmable device measures the time t-high by sampling the
29 * tachometer every t-sample (with the default value 11.32 uS) and increment
31 * RPM = 15 / (t-sample * (K + Regval)), where:
33 * - 0xff - represents tachometer fault;
34 * - 0xfe - represents tachometer minimum value , which is 4444 RPM;
35 * - 0x00 - represents tachometer maximum value , which is 300000 RPM;
39 * used: RPM = 15 / ((Regval + K) * 11.32) * 10^(-6)), which in the
42 * - for Regval 0x00, RPM will be 15000000 * 100 / (44 * 1132) = 30115;
[all …]
/linux/drivers/gpu/drm/pl111/
H A Dpl111_drm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
8 * Copyright (c) 2006-2008 Intel Corporation
16 #include <linux/clk-provider.h>
27 * CLCD Controller Internal Register addresses
104 * struct pl111_variant_data - encodes IP differences
110 * @broken_clockdivider: the clock divider is broken and we need to
111 * use the supplied clock directly
144 /* The pixel clock (a reference to our clock divider off of CLCDCLK). */
146 /* pl111's internal clock divider. */
/linux/Documentation/devicetree/bindings/timer/
H A Dnxp,sysctr-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bai Ping <ping.bai@nxp.com>
15 etc. it is intended for use in applications where the counter
22 - enum:
23 - nxp,imx95-sysctr-timer
24 - nxp,sysctr-timer
25 - items:
[all …]
/linux/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
39 /* extend the public set of clocks by adding internal slots for management */
65 /* internal, symbolic spec for the number of slots */
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
292 val &= (1 << len) - 1; in get_bit_field()
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
350 cpmf = get_bit_field(&clkregs->spmr, 16, 4); in get_cpmf_mult_x2()
[all …]
/linux/drivers/gpu/drm/amd/display/include/
H A Dbios_parser_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
197 /* Input: Signal Type - to be converted to Encoder mode */
207 /* Output: If non-zero, this refDiv value should be used to calculate
210 /* Output: If non-zero, this postDiv value should be used to calculate
220 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */
225 /* Calculated Reference divider of Display PLL */
227 /* Calculated Feedback divider of Display PLL */
229 /* Calculated Fractional Feedback divider of Display PLL */
[all …]
/linux/drivers/iio/imu/inv_mpu6050/
H A Dinv_mpu_aux.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 TDK-InvenSense, Inc.
22 /* use 50hz frequency for xfer */ in inv_mpu_i2c_master_xfer()
32 ret = regmap_write(st->map, st->reg->sample_rate_div, d); in inv_mpu_i2c_master_xfer()
37 user_ctrl = st->chip_config.user_ctrl | INV_MPU6050_BIT_I2C_MST_EN; in inv_mpu_i2c_master_xfer()
38 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); in inv_mpu_i2c_master_xfer()
42 /* wait for xfer: 1 period + half-period margin */ in inv_mpu_i2c_master_xfer()
46 user_ctrl = st->chip_config.user_ctrl; in inv_mpu_i2c_master_xfer()
47 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); in inv_mpu_i2c_master_xfer()
52 d = st->chip_config.divider; in inv_mpu_i2c_master_xfer()
[all …]
/linux/drivers/clk/sunxi/
H A Dclk-a20-gmac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
29 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
34 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
35 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
36 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
39 * The external 125 MHz reference is optional, i.e. GMAC can use its
40 * internal TX clock just fine. The A31 GMAC clock module does not have
[all …]
/linux/drivers/clk/sophgo/
H A Dclk-sg2042-clkgen.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
19 #include "clk-sg2042.h"
23 #define R_PLL_STAT (0xC0 - R_PLL_BEGIN)
24 #define R_PLL_CLKEN_CONTROL (0xC4 - R_PLL_BEGIN)
25 #define R_MPLL_CONTROL (0xE8 - R_PLL_BEGIN)
26 #define R_FPLL_CONTROL (0xF4 - R_PLL_BEGIN)
27 #define R_DPLL0_CONTROL (0xF8 - R_PLL_BEGIN)
28 #define R_DPLL1_CONTROL (0xFC - R_PLL_BEGIN)
[all …]
/linux/drivers/gpu/ipu-v3/
H A Dipu-di.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
14 #include <video/imx-ipu-v3.h>
15 #include "ipu-prv.h"
76 #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1))
77 #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1))
78 #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2))
125 return readl(di->base + offset); in ipu_di_read()
130 writel(value, di->base + offset); in ipu_di_write()
166 if ((c->run_count >= 0x1000) || (c->offset_count >= 0x1000) || in ipu_di_sync_config()
[all …]
/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0
33 * [11] mipi divider clk selection.
34 * 1: select the mipi DDRCLKHS from clock divider.
36 * [10] mipi clock divider control.
38 * [9] mipi divider output enable.
39 * [8] mipi divider counter enable.
46 * [1] write 1 to sync the txclkesc input. the internal logic have to
47 * use txclkesc to decide Txvalid and Txready.
53 * 1: from register. 0: use clk lane state machine.
188 ret = phy_init(priv->analog); in phy_meson_axg_mipi_dphy_init()
[all …]
/linux/drivers/iio/adc/
H A Dstm32-dfsdm-core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
24 #include "stm32-dfsdm.h"
27 * struct stm32_dfsdm_dev_data - DFSDM compatible configuration data
97 unsigned int spi_clk_out_div; /* SPI clkout divider value */
114 ret = clk_prepare_enable(priv->clk); in stm32_dfsdm_clk_prepare_enable()
115 if (ret || !priv->aclk) in stm32_dfsdm_clk_prepare_enable()
118 ret = clk_prepare_enable(priv->aclk); in stm32_dfsdm_clk_prepare_enable()
120 clk_disable_unprepare(priv->clk); in stm32_dfsdm_clk_prepare_enable()
129 clk_disable_unprepare(priv->aclk); in stm32_dfsdm_clk_disable_unprepare()
[all …]
/linux/sound/soc/fsl/
H A Dfsl_asrc.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/dma-mapping.h>
14 #include <linux/dma/imx-dma.h>
26 dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
29 dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
32 dev_warn(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
110 * According to RM, the divider range is 1 ~ 8,
114 1, 2, 4, 8, 16, 32, 64, 128, /* divider = 1 */
115 2, 4, 8, 16, 32, 64, 128, 256, /* divider = 2 */
116 3, 6, 12, 24, 48, 96, 192, 384, /* divider = 3 */
[all …]
/linux/drivers/clk/davinci/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
78 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
85 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
89 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
95 * struct davinci_pll_clk - Main PLL clock (aka PLLOUT)
120 mult = readl(pll->base + PLLM) & pll->pllm_mask; in davinci_pll_recalc_rate()
[all …]
/linux/drivers/comedi/drivers/
H A Ddt2811.c1 // SPDX-License-Identifier: GPL-2.0+
5 * COMEDI - Linux Control and Measurement Device Interface
13 * Devices: [Data Translation] DT2811-PGL (dt2811-pgl), DT2811-PGH (dt2811-pgh)
17 * [0] - I/O port base address
18 * [1] - IRQ (optional, needed for async command support)
19 * [2] - A/D reference (# of analog inputs)
20 * 0 = single-ended (16 channels)
22 * 2 = pseudo-differential (16 channels)
23 * [3] - A/D range (deprecated, see below)
24 * [4] - D/A 0 range (deprecated, see below)
[all …]
/linux/sound/soc/ti/
H A Domap-mcbsp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
23 #include "omap-mcbsp-priv.h"
24 #include "omap-mcbsp.h"
25 #include "sdma-pcm.h"
40 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id); in omap_mcbsp_dump_reg()
41 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2)); in omap_mcbsp_dump_reg()
42 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1)); in omap_mcbsp_dump_reg()
43 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2)); in omap_mcbsp_dump_reg()
44 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1)); in omap_mcbsp_dump_reg()
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
191 #pragma pack(1) // BIOS data must use byte alignment
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
300 … //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
[all …]
/linux/drivers/clocksource/
H A Dtimer-microchip-pit64b.c1 // SPDX-License-Identifier: GPL-2.0
3 * 64-bit Periodic Interval Timer driver
51 * struct mchp_pit64b_timer - PIT64B timer data structure
65 * struct mchp_pit64b_clkevt - PIT64B clockevent data structure
79 * struct mchp_pit64b_clksrc - PIT64B clocksource data structure
127 writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); in mchp_pit64b_reset()
128 writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR); in mchp_pit64b_reset()
129 writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR); in mchp_pit64b_reset()
130 writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR); in mchp_pit64b_reset()
131 writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER); in mchp_pit64b_reset()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgm20b.c7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
89 #define DFS_DET_RANGE 6 /* -2^6 ... 2^6-1 */
90 #define SDM_DIN_RANGE 12 /* -2^12 ... 2^12-1 */
99 .coeff_slope = -165230,
136 /* safe frequency we can use at minimum voltage */
162 struct nvkm_subdev *subdev = &clk->base.base.subdev; in gm20b_pllg_read_mnp()
163 struct nvkm_device *device = subdev->device; in gm20b_pllg_read_mnp()
166 gk20a_pllg_read_mnp(&clk->base, &pll->base); in gm20b_pllg_read_mnp()
168 pll->sdm_din = (val >> GPCPLL_CFG2_SDM_DIN_SHIFT) & in gm20b_pllg_read_mnp()
[all …]
/linux/include/linux/mtd/
H A Dsh_flctl.h1 /* SPDX-License-Identifier: GPL-2.0
18 #define FLCMNCR(f) (f->reg + 0x0)
19 #define FLCMDCR(f) (f->reg + 0x4)
20 #define FLCMCDR(f) (f->reg + 0x8)
21 #define FLADR(f) (f->reg + 0xC)
22 #define FLADR2(f) (f->reg + 0x3C)
23 #define FLDATAR(f) (f->reg + 0x10)
24 #define FLDTCNTR(f) (f->reg + 0x14)
25 #define FLINTDMACR(f) (f->reg + 0x18)
26 #define FLBSYTMR(f) (f->reg + 0x1C)
[all …]

12345