Lines Matching +full:use +full:- +full:internal +full:- +full:divider
1 /* SPDX-License-Identifier: GPL-2.0
18 #define FLCMNCR(f) (f->reg + 0x0)
19 #define FLCMDCR(f) (f->reg + 0x4)
20 #define FLCMCDR(f) (f->reg + 0x8)
21 #define FLADR(f) (f->reg + 0xC)
22 #define FLADR2(f) (f->reg + 0x3C)
23 #define FLDATAR(f) (f->reg + 0x10)
24 #define FLDTCNTR(f) (f->reg + 0x14)
25 #define FLINTDMACR(f) (f->reg + 0x18)
26 #define FLBSYTMR(f) (f->reg + 0x1C)
27 #define FLBSYCNT(f) (f->reg + 0x20)
28 #define FLDTFIFO(f) (f->reg + 0x24)
29 #define FLECFIFO(f) (f->reg + 0x28)
30 #define FLTRCR(f) (f->reg + 0x2C)
31 #define FLHOLDCR(f) (f->reg + 0x38)
32 #define FL4ECCRESULT0(f) (f->reg + 0x80)
33 #define FL4ECCRESULT1(f) (f->reg + 0x84)
34 #define FL4ECCRESULT2(f) (f->reg + 0x88)
35 #define FL4ECCRESULT3(f) (f->reg + 0x8C)
36 #define FL4ECCCR(f) (f->reg + 0x90)
37 #define FL4ECCCNT(f) (f->reg + 0x94)
38 #define FLERRADR(f) (f->reg + 0x98)
61 * to control the clock divider used between the High-Speed Peripheral Clock
62 * and the FLCTL internal clock. If so, use CLK_8_BIT_xxx for connecting 8 bit
64 * bit version the divider is seperate for the pulse width of high and low