xref: /linux/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml (revision 6190d0fa18995b8bcc6b9a26913bb8390bda8396) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11  - Marek Szyprowski <m.szyprowski@samsung.com>
12  - Sylwester Nawrocki <s.nawrocki@samsung.com>
13
14description: |
15  For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
16  compatible PHYs, the second cell in the PHY specifier identifies the
17  PHY id, which is interpreted as follows::
18    0 - UTMI+ type phy,
19    1 - PIPE3 type phy.
20
21  For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
22  'usbdrd_phy' nodes should have numbered alias in the aliases node, in the
23  form of usbdrdphyN, N = 0, 1... (depending on number of controllers).
24
25properties:
26  compatible:
27    enum:
28      - google,gs101-usb31drd-phy
29      - samsung,exynos2200-usb32drd-phy
30      - samsung,exynos5250-usbdrd-phy
31      - samsung,exynos5420-usbdrd-phy
32      - samsung,exynos5433-usbdrd-phy
33      - samsung,exynos7-usbdrd-phy
34      - samsung,exynos7870-usbdrd-phy
35      - samsung,exynos850-usbdrd-phy
36      - samsung,exynos990-usbdrd-phy
37
38  clocks:
39    minItems: 1
40    maxItems: 5
41
42  clock-names:
43    minItems: 1
44    maxItems: 5
45    description: |
46      Typically two clocks:
47        - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
48          for register access.
49        - PHY reference clock (usually crystal clock), used for PHY operations,
50          associated by phy name. It is used to determine bit values for clock
51          settings register.  For Exynos5420 this is given as 'sclk_usbphy30'
52          in the CMU. It's not needed for Exynos2200.
53
54  "#phy-cells":
55    const: 1
56
57  phys:
58    maxItems: 1
59    description:
60      USBDRD-underlying high-speed PHY
61
62  phy-names:
63    const: hs
64
65  port:
66    $ref: /schemas/graph.yaml#/properties/port
67    description:
68      Any connector to the data bus of this controller should be modelled using
69      the OF graph bindings specified.
70
71  reg:
72    minItems: 1
73    maxItems: 3
74
75  reg-names:
76    minItems: 1
77    items:
78      - const: phy
79      - const: pcs
80      - const: pma
81
82  samsung,pmu-syscon:
83    $ref: /schemas/types.yaml#/definitions/phandle
84    description:
85      Phandle to PMU system controller interface.
86
87  vbus-supply:
88    description:
89      VBUS power source.
90
91  vbus-boost-supply:
92    description:
93      VBUS Boost 5V power source.
94
95  pll-supply:
96    description: Power supply for the USB PLL.
97
98  dvdd-usb20-supply:
99    description: DVDD power supply for the USB 2.0 phy.
100
101  vddh-usb20-supply:
102    description: VDDh power supply for the USB 2.0 phy.
103
104  vdd33-usb20-supply:
105    description: 3.3V power supply for the USB 2.0 phy.
106
107  vdda-usbdp-supply:
108    description: VDDa power supply for the USB DP phy.
109
110  vddh-usbdp-supply:
111    description: VDDh power supply for the USB DP phy.
112
113required:
114  - compatible
115  - clocks
116  - clock-names
117  - "#phy-cells"
118  - reg
119  - samsung,pmu-syscon
120
121allOf:
122  - if:
123      properties:
124        compatible:
125          contains:
126            const: google,gs101-usb31drd-phy
127    then:
128      allOf:
129        - $ref: /schemas/usb/usb-switch.yaml#
130        - $ref: /schemas/usb/usb-switch-ports.yaml#
131
132      properties:
133        clocks:
134          items:
135            - description: Gate of main PHY clock
136            - description: Gate of PHY reference clock
137            - description: Gate of control interface AXI clock
138            - description: Gate of control interface APB clock
139            - description: Gate of SCL APB clock
140
141        clock-names:
142          items:
143            - const: phy
144            - const: ref
145            - const: ctrl_aclk
146            - const: ctrl_pclk
147            - const: scl_pclk
148
149        reg:
150          minItems: 3
151
152        reg-names:
153          minItems: 3
154
155      required:
156        - reg-names
157        - orientation-switch
158        - port
159        - pll-supply
160        - dvdd-usb20-supply
161        - vddh-usb20-supply
162        - vdd33-usb20-supply
163        - vdda-usbdp-supply
164        - vddh-usbdp-supply
165
166  - if:
167      properties:
168        compatible:
169          contains:
170            enum:
171              - samsung,exynos2200-usb32drd-phy
172    then:
173      properties:
174        clocks:
175          maxItems: 1
176        clock-names:
177          items:
178            - const: phy
179        reg:
180          maxItems: 1
181        reg-names:
182          maxItems: 1
183      required:
184        - phys
185        - phy-names
186
187  - if:
188      properties:
189        compatible:
190          contains:
191            enum:
192              - samsung,exynos5433-usbdrd-phy
193              - samsung,exynos7-usbdrd-phy
194    then:
195      properties:
196        clocks:
197          minItems: 5
198          maxItems: 5
199
200        clock-names:
201          items:
202            - const: phy
203            - const: ref
204            - const: phy_utmi
205            - const: phy_pipe
206            - const: itp
207
208        reg:
209          maxItems: 1
210
211        reg-names:
212          maxItems: 1
213
214  - if:
215      properties:
216        compatible:
217          contains:
218            enum:
219              - samsung,exynos5250-usbdrd-phy
220              - samsung,exynos5420-usbdrd-phy
221              - samsung,exynos7870-usbdrd-phy
222              - samsung,exynos850-usbdrd-phy
223              - samsung,exynos990-usbdrd-phy
224    then:
225      properties:
226        clocks:
227          minItems: 2
228          maxItems: 2
229
230        clock-names:
231          items:
232            - const: phy
233            - const: ref
234
235        reg:
236          maxItems: 1
237
238        reg-names:
239          maxItems: 1
240
241unevaluatedProperties: false
242
243examples:
244  - |
245    #include <dt-bindings/clock/exynos5420.h>
246
247    phy@12100000 {
248        compatible = "samsung,exynos5420-usbdrd-phy";
249        reg = <0x12100000 0x100>;
250        #phy-cells = <1>;
251        clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
252        clock-names = "phy", "ref";
253        samsung,pmu-syscon = <&pmu_system_controller>;
254        vbus-supply = <&usb300_vbus_reg>;
255    };
256