xref: /linux/Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml (revision 502d45774af09f1c681c754c4b7cdfb5d7f72fd9) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on Glymur SoC
8
9maintainers:
10  - Taniya Das <taniya.das@oss.qualcomm.com>
11
12description: |
13  Qualcomm global clock control module provides the clocks, resets and power
14  domains on Glymur SoC.
15
16  See also: include/dt-bindings/clock/qcom,glymur-gcc.h
17
18properties:
19  compatible:
20    const: qcom,glymur-gcc
21
22  clocks:
23    items:
24      - description: Board XO source
25      - description: Board XO_A source
26      - description: Sleep clock source
27      - description: USB 0 Phy DP0 GMUX clock source
28      - description: USB 0 Phy DP1 GMUX clock source
29      - description: USB 0 Phy PCIE PIPEGMUX clock source
30      - description: USB 0 Phy PIPEGMUX clock source
31      - description: USB 0 Phy SYS PCIE PIPEGMUX clock source
32      - description: USB 1 Phy DP0 GMUX 2 clock source
33      - description: USB 1 Phy DP1 GMUX 2 clock source
34      - description: USB 1 Phy PCIE PIPEGMUX clock source
35      - description: USB 1 Phy PIPEGMUX clock source
36      - description: USB 1 Phy SYS PCIE PIPEGMUX clock source
37      - description: USB 2 Phy DP0 GMUX 2 clock source
38      - description: USB 2 Phy DP1 GMUX 2 clock source
39      - description: USB 2 Phy PCIE PIPEGMUX clock source
40      - description: USB 2 Phy PIPEGMUX clock source
41      - description: USB 2 Phy SYS PCIE PIPEGMUX clock source
42      - description: PCIe 3a pipe clock
43      - description: PCIe 3b pipe clock
44      - description: PCIe 4 pipe clock
45      - description: PCIe 5 pipe clock
46      - description: PCIe 6 pipe clock
47      - description: QUSB4 0 PHY RX 0 clock source
48      - description: QUSB4 0 PHY RX 1 clock source
49      - description: QUSB4 1 PHY RX 0 clock source
50      - description: QUSB4 1 PHY RX 1 clock source
51      - description: QUSB4 2 PHY RX 0 clock source
52      - description: QUSB4 2 PHY RX 1 clock source
53      - description: UFS PHY RX Symbol 0 clock source
54      - description: UFS PHY RX Symbol 1 clock source
55      - description: UFS PHY TX Symbol 0 clock source
56      - description: USB3 PHY 0 pipe clock source
57      - description: USB3 PHY 1 pipe clock source
58      - description: USB3 PHY 2 pipe clock source
59      - description: USB3 UNI PHY pipe 0 clock source
60      - description: USB3 UNI PHY pipe 1 clock source
61      - description: USB4 PHY 0 pcie pipe clock source
62      - description: USB4 PHY 0 Max pipe clock source
63      - description: USB4 PHY 1 pcie pipe clock source
64      - description: USB4 PHY 1 Max pipe clock source
65      - description: USB4 PHY 2 pcie pipe clock source
66      - description: USB4 PHY 2 Max pipe clock source
67
68  power-domains:
69    description:
70      A phandle and PM domain specifier for the CX power domain.
71    maxItems: 1
72
73required:
74  - compatible
75  - clocks
76  - power-domains
77  - '#power-domain-cells'
78
79allOf:
80  - $ref: qcom,gcc.yaml#
81
82unevaluatedProperties: false
83
84examples:
85  - |
86    #include <dt-bindings/clock/qcom,rpmh.h>
87    #include <dt-bindings/power/qcom-rpmpd.h>
88    clock-controller@100000 {
89      compatible = "qcom,glymur-gcc";
90      reg = <0x100000 0x1f9000>;
91      clocks = <&rpmhcc RPMH_CXO_CLK>,
92               <&rpmhcc RPMH_CXO_CLK_A>,
93               <&sleep_clk>,
94               <&usb_0_phy_dp0_gmux>,
95               <&usb_0_phy_dp1_gmux>,
96               <&usb_0_phy_pcie_pipegmux>,
97               <&usb_0_phy_pipegmux>,
98               <&usb_0_phy_sys_pcie_pipegmux>,
99               <&usb_1_phy_dp0_gmux_2>,
100               <&usb_1_phy_dp1_gmux_2>,
101               <&usb_1_phy_pcie_pipegmux>,
102               <&usb_1_phy_pipegmux>,
103               <&usb_1_phy_sys_pcie_pipegmux>,
104               <&usb_2_phy_dp0_gmux 2>,
105               <&usb_2_phy_dp1_gmux 2>,
106               <&usb_2_phy_pcie_pipegmux>,
107               <&usb_2_phy_pipegmux>,
108               <&usb_2_phy_sys_pcie_pipegmux>,
109               <&pcie_3a_pipe>, <&pcie_3b_pipe>,
110               <&pcie_4_pipe>, <&pcie_5_pipe>,
111               <&pcie_6_pipe>,
112               <&qusb4_0_phy_rx_0>, <&qusb4_0_phy_rx_1>,
113               <&qusb4_1_phy_rx_0>, <&qusb4_1_phy_rx_1>,
114               <&qusb4_2_phy_rx_0>, <&qusb4_2_phy_rx_1>,
115               <&ufs_phy_rx_symbol_0>, <&ufs_phy_rx_symbol_1>,
116               <&ufs_phy_tx_symbol_0>,
117               <&usb3_phy_0_pipe>, <&usb3_phy_1_pipe>,
118               <&usb3_phy_2_pipe>,
119               <&usb3_uni_phy_pipe_0>, <&usb3_uni_phy_pipe_1>,
120               <&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>,
121               <&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>,
122               <&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>;
123      power-domains = <&rpmhpd RPMHPD_CX>;
124      #clock-cells = <1>;
125      #reset-cells = <1>;
126      #power-domain-cells = <1>;
127    };
128
129...
130