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/linux/drivers/phy/broadcom/
H A Dphy-bcm-ns-usb3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom Northstar USB 3.0 PHY Driver
22 #include <linux/phy/phy.h>
54 struct phy *phy; member
59 .compatible = "brcm,ns-ax-usb3-phy",
63 .compatible = "brcm,ns-bx-usb3-phy",
69 static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg,
72 static int bcm_ns_usb3_phy_init_ns_bx(struct bcm_ns_usb3 *usb3) in bcm_ns_usb3_phy_init_ns_bx() argument
76 /* USB3 PLL Block */ in bcm_ns_usb3_phy_init_ns_bx()
77 err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, in bcm_ns_usb3_phy_init_ns_bx()
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
[all …]
H A Dsocionext,uniphier-usb3ss-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
[all …]
H A Dsocionext,uniphier-usb3hs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
[all …]
H A Dbcm-ns-usb3-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/bcm-ns-usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Northstar USB 3.0 PHY
10 Initialization of USB 3.0 PHY depends on Northstar version. There are currently
18 - Rafał Miłecki <rafal@milecki.pl>
23 - brcm,ns-ax-usb3-phy
24 - brcm,ns-bx-usb3-phy
30 usb3-dmp-syscon:
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Damlogic,g12a-usb3-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/amlogic,g12a-usb3-pcie-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic G12A USB3 + PCIE Combo PHY
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - amlogic,g12a-usb3-pcie-phy
24 clock-names:
26 - const: ref_clk
31 reset-names:
[all …]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dallwinner,sun50i-h6-usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb3-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Allwinner H6 USB3 PHY
11 - Ondrej Jirman <megous@megous.com>
16 - allwinner,sun50i-h6-usb3-phy
27 "#phy-cells":
31 - compatible
32 - reg
[all …]
H A Dsocionext,uniphier-usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB2 PHY
10 This describes the devicetree bindings for PHY interface built into
12 Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3
13 controller doesn't include its own High-Speed PHY. This needs to specify
14 USB2 PHY instead of USB3 HS-PHY.
17 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
[all …]
/linux/drivers/phy/tegra/
H A Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/phy/phy.h>
13 #include <linux/phy/tegra/xusb.h>
24 static struct phy *tegra_xusb_pad_of_xlate(struct device *dev, in tegra_xusb_pad_of_xlate()
28 struct phy *phy = NULL; in tegra_xusb_pad_of_xlate() local
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
[all …]
H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
10 #include <linux/phy/phy.h>
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
283 writel(value, priv->ao_regs + offset); in ao_writel()
288 return readl(priv->ao_regs + offset); in ao_readl()
297 /* USB 2.0 UTMI PHY support */
307 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
309 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
310 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
[all …]
/linux/Documentation/devicetree/bindings/soc/socionext/
H A Dsocionext,uniphier-dwc3-glue.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
15 USB3.0 component.
20 - enum:
21 - socionext,uniphier-pro4-dwc3-glue
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234-p3768-0000+p3767.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-bindings/input/gpio-keys.h>
6 #include "tegra234-p3767.dtsi"
17 stdout-path = "serial0:115200n8";
22 compatible = "nvidia,tegra194-hsuart";
23 reset-names = "serial";
28 compatible = "nvidia,tegra194-hsuart";
29 reset-names = "serial";
41 vcc-supply = <&vdd_1v8_sys>;
[all …]
H A Dtegra234-p3740-0002+p3701-0008.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/sound/rt5640.h>
7 #include "tegra234-p3701-0008.dtsi"
11 compatible = "nvidia,p3740-0002+p3701-0008", "nvidia,p3701-0008", "nvidia,tegra234";
19 stdout-path = "serial0:115200n8";
29 dai-format = "i2s";
30 remote-endpoint = <&rt5640_ep>;
[all …]
/linux/drivers/phy/socionext/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # PHY drivers for Socionext platforms.
7 tristate "UniPhier USB2 PHY driver"
13 Enable this to support USB PHY implemented on USB2 controller
15 with USB 2.0 PHY that is part of the UniPhier SoC.
16 In case of Pro4, it is necessary to specify this USB2 PHY instead
17 of USB3 HS-PHY.
20 tristate "UniPhier USB3 PHY driver"
25 Enable this to support USB PHY implemented in USB3 controller
26 on UniPhier SoCs. This controller supports USB3.0 and lower speed.
[all …]
H A Dphy-uniphier-usb3ss.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-usb3ss.c - SS-PHY driver for Socionext UniPhier USB3 controller
4 * Copyright 2015-2018 Socionext Inc.
19 #include <linux/phy/phy.h>
73 writel(data, priv->base + SSPHY_TESTI); in uniphier_u3ssphy_testio_write()
74 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write()
75 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write()
82 u8 field_mask = GENMASK(p->field.msb, p->field.lsb); in uniphier_u3ssphy_set_param()
87 val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no); in uniphier_u3ssphy_set_param()
89 val = readl(priv->base + SSPHY_TESTO) & TESTO_DAT_MASK; in uniphier_u3ssphy_set_param()
[all …]
H A Dphy-uniphier-usb3hs.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-usb3hs.c - HS-PHY driver for Socionext UniPhier USB3 controller
4 * Copyright 2015-2018 Socionext Inc.
17 #include <linux/nvmem-consumer.h>
20 #include <linux/phy/phy.h>
66 #define trim_param_is_valid(p) ((p)->rterm || (p)->sel_t || (p)->hs_i)
92 *pconfig |= FIELD_PREP(HSPHY_CFG0_RTERM_MASK, pt->rterm); in uniphier_u3hsphy_trim_ld20()
95 *pconfig |= FIELD_PREP(HSPHY_CFG0_SEL_T_MASK, pt->sel_t); in uniphier_u3hsphy_trim_ld20()
98 *pconfig |= FIELD_PREP(HSPHY_CFG0_HS_I_MASK, pt->hs_i); in uniphier_u3hsphy_trim_ld20()
107 cell = devm_nvmem_cell_get(priv->dev, name); in uniphier_u3hsphy_get_nvparam()
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,glymur-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <taniya.das@oss.qualcomm.com>
16 See also: include/dt-bindings/clock/qcom,glymur-gcc.h
20 const: qcom,glymur-gcc
24 - description: Board XO source
25 - description: Board XO_A source
26 - description: Sleep clock source
[all …]
/linux/Documentation/devicetree/bindings/soc/hisilicon/
H A Dhisilicon,hi3660-usb3-otg-bc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
15 - const: hisilicon,hi3660-usb3-otg-bc
16 - const: syscon
17 - const: simple-mfd
22 usb-phy:
23 $ref: /schemas/phy/hisilicon,hi3660-usb3.yaml
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
22 The DWC3 Glue controls the PHY routing and power, an interrupt line is
[all …]
H A Dmediatek,mtk-xhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek USB3 xHCI
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
[all …]
/linux/drivers/phy/mediatek/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Mediatek devices
6 tristate "MediaTek PCIe-PHY Driver"
11 Say 'Y' here to add support for MediaTek PCIe PHY driver.
12 This driver create the basic PHY instance and provides initialize
17 tristate "MediaTek 10GE SerDes XFI T-PHY driver"
22 Say 'Y' here to add support for MediaTek XFI T-PHY driver.
23 The driver provides access to the Ethernet SerDes T-PHY supporting
28 tristate "MediaTek T-PHY Driver"
34 Say 'Y' here to add support for MediaTek T-PHY driver,
[all …]
/linux/drivers/phy/qualcomm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Qualcomm and Atheros platforms
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm eDP PHY driver"
28 Enable this driver to support the Qualcomm eDP PHY found in various
32 tristate "Qualcomm IPQ4019 USB PHY driver"
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
39 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
[all …]

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