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/linux/drivers/usb/gadget/udc/
H A Drenesas_usb3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas USB3.0 Peripheral driver (USB gadget)
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
13 #include <linux/extcon-provider.h>
37 #define USB3_DMA_CH0_CON(n) (0x030 + ((n) - 1) * 0x10) /* n = 1 to 4 */
38 #define USB3_DMA_CH0_PRD_ADR(n) (0x034 + ((n) - 1) * 0x10) /* n = 1 to 4 */
43 #define USB3_DRD_CON(p) ((p)->is_rzv2m ? 0x400 : 0x218)
50 #define USB3_USB_OTG_STA(p) ((p)->is_rzv2m ? 0x410 : 0x268)
51 #define USB3_USB_OTG_INT_STA(p) ((p)->is_rzv2m ? 0x414 : 0x26c)
[all …]
/linux/drivers/phy/broadcom/
H A Dphy-bcm-ns-usb3.c1 // SPDX-License-Identifier: GPL-2.0-only
59 .compatible = "brcm,ns-ax-usb3-phy",
63 .compatible = "brcm,ns-bx-usb3-phy",
69 static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg,
72 static int bcm_ns_usb3_phy_init_ns_bx(struct bcm_ns_usb3 *usb3) in bcm_ns_usb3_phy_init_ns_bx() argument
76 /* USB3 PLL Block */ in bcm_ns_usb3_phy_init_ns_bx()
77 err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, in bcm_ns_usb3_phy_init_ns_bx()
79 if (err < 0) in bcm_ns_usb3_phy_init_ns_bx()
83 bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLL_CONTROL, 0x1000); in bcm_ns_usb3_phy_init_ns_bx()
86 bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL0, 0x6400); in bcm_ns_usb3_phy_init_ns_bx()
[all …]
/linux/drivers/usb/cdns3/
H A DKconfig4 select USB_XHCI_PLATFORM if USB_XHCI_HCD
7 Say Y here if your system has a Cadence USBSS or USBSSP
8 dual-role controller.
9 It supports: dual-role switch, Host-only, and Peripheral-only.
14 if USB_CDNS_SUPPORT
17 tristate "Cadence USB3 Dual-Role Controller"
20 Say Y here if your system has a Cadence USB3 dual-role controller.
21 It supports: dual-role switch, Host-only, and Peripheral-only.
23 If you choose to build this driver is a dynamically linked
27 if USB_CDNS3
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/linux/Documentation/devicetree/bindings/phy/
H A Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
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H A Dsocionext,uniphier-usb3ss-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-ssphy
[all …]
H A Dsocionext,uniphier-usb3hs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
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H A Dqcom,sc8280xp-qmp-usb43dp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
19 - qcom,sar2130p-qmp-usb3-dp-phy
20 - qcom,sc7180-qmp-usb3-dp-phy
21 - qcom,sc7280-qmp-usb3-dp-phy
22 - qcom,sc8180x-qmp-usb3-dp-phy
[all …]
H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
/linux/drivers/phy/tegra/
H A Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
44 if (phy == NULL) in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
[all …]
H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
282 writel(value, priv->ao_regs + offset); in ao_writel()
287 return readl(priv->ao_regs + offset); in ao_readl()
305 if (!usb2) in tegra186_usb2_lane_probe()
306 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
308 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
309 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
310 usb2->base.index = index; in tegra186_usb2_lane_probe()
[all …]
/linux/fs/ufs/
H A Dutil.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 return &cpi->c_ubh; in UCPI_UBH()
23 return &spi->s_ubh; in USPI_UBH()
33 struct ufs_super_block_third *usb3) in ufs_get_fs_state() argument
35 switch (UFS_SB(sb)->s_flags & UFS_ST_MASK) { in ufs_get_fs_state()
37 if (fs32_to_cpu(sb, usb3->fs_postblformat) == UFS_42POSTBLFMT) in ufs_get_fs_state()
38 return fs32_to_cpu(sb, usb1->fs_u0.fs_sun.fs_state); in ufs_get_fs_state()
41 return fs32_to_cpu(sb, usb3->fs_un2.fs_sun.fs_state); in ufs_get_fs_state()
43 return fs32_to_cpu(sb, usb1->fs_u1.fs_sunx86.fs_state); in ufs_get_fs_state()
46 return fs32_to_cpu(sb, usb3->fs_un2.fs_44.fs_state); in ufs_get_fs_state()
[all …]
H A Dsuper.c1 // SPDX-License-Identifier: GPL-2.0-only
16 * Laboratoire MASI - Institut Blaise Pascal
25 * Big-endian to little-endian byte-swapping/bitmaps by
35 * Adrian Rodriguez (adrian@franklins-tower.rutgers.edu)
48 * Francois-Rene Rideau <fare@tunes.org>
52 * on code by Martin von Loewis <martin@mira.isdn.cs.tu-berlin.de>.
84 #include <linux/backing-dev.h>
101 struct ufs_sb_private_info *uspi = UFS_SB(sb)->s_uspi; in ufs_nfs_get_inode()
104 if (ino < UFS_ROOTINO || ino > (u64)uspi->s_ncg * uspi->s_ipg) in ufs_nfs_get_inode()
105 return ERR_PTR(-ESTALE); in ufs_nfs_get_inode()
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dsocionext,uniphier-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/socionext,uniphier-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This regulator controls VBUS and belongs to USB3 glue layer. Before using
15 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17 # USB3 Controller
22 - socionext,uniphier-pro4-usb3-regulator
23 - socionext,uniphier-pro5-usb3-regulator
24 - socionext,uniphier-pxs2-usb3-regulator
[all …]
/linux/Documentation/devicetree/bindings/reset/
H A Dsocionext,uniphier-glue-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-reset
22 - socionext,uniphier-pro5-usb3-reset
23 - socionext,uniphier-pxs2-usb3-reset
24 - socionext,uniphier-ld20-usb3-reset
25 - socionext,uniphier-pxs3-usb3-reset
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-s922x-khadas-vim3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-g12b-s922x.dtsi"
11 #include "meson-khadas-vim3.dtsi"
12 #include "meson-g12b-khadas-vim3.dtsi"
19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
21 * an USB3.0 Type A connector and a M.2 Key M slot.
23 * the USB3.0 controller and the PCIe Controller, thus only
25 * If the MCU is configured to mux the PCIe/USB3.0 differential lines
27 * USB3.0 from the USB Complex and enable the PCIe controller.
[all …]
H A Dmeson-g12b-a311d-khadas-vim3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-g12b-a311d.dtsi"
11 #include "meson-khadas-vim3.dtsi"
12 #include "meson-g12b-khadas-vim3.dtsi"
19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
21 * an USB3.0 Type A connector and a M.2 Key M slot.
23 * the USB3.0 controller and the PCIe Controller, thus only
25 * If the MCU is configured to mux the PCIe/USB3.0 differential lines
27 * USB3.0 from the USB Complex and enable the PCIe controller.
[all …]
H A Dmeson-sm1-khadas-vim3l.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-sm1.dtsi"
10 #include "meson-khadas-vim3.dtsi"
11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
17 vddcpu: regulator-vddcpu {
21 compatible = "pwm-regulator";
23 regulator-name = "VDDCPU";
24 regulator-min-microvolt = <690000>;
25 regulator-max-microvolt = <1050000>;
[all …]
/linux/drivers/phy/socionext/
H A Dphy-uniphier-usb3ss.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-usb3ss.c - SS-PHY driver for Socionext UniPhier USB3 controller
4 * Copyright 2015-2018 Socionext Inc.
73 writel(data, priv->base + SSPHY_TESTI); in uniphier_u3ssphy_testio_write()
74 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write()
75 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write()
82 u8 field_mask = GENMASK(p->field.msb, p->field.lsb); in uniphier_u3ssphy_set_param()
87 val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no); in uniphier_u3ssphy_set_param()
89 val = readl(priv->base + SSPHY_TESTO) & TESTO_DAT_MASK; in uniphier_u3ssphy_set_param()
93 data = field_mask & (p->value << p->field.lsb); in uniphier_u3ssphy_set_param()
[all …]
H A Dphy-uniphier-usb3hs.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-usb3hs.c - HS-PHY driver for Socionext UniPhier USB3 controller
4 * Copyright 2015-2018 Socionext Inc.
17 #include <linux/nvmem-consumer.h>
66 #define trim_param_is_valid(p) ((p)->rterm || (p)->sel_t || (p)->hs_i)
92 *pconfig |= FIELD_PREP(HSPHY_CFG0_RTERM_MASK, pt->rterm); in uniphier_u3hsphy_trim_ld20()
95 *pconfig |= FIELD_PREP(HSPHY_CFG0_SEL_T_MASK, pt->sel_t); in uniphier_u3hsphy_trim_ld20()
98 *pconfig |= FIELD_PREP(HSPHY_CFG0_HS_I_MASK, pt->hs_i); in uniphier_u3hsphy_trim_ld20()
107 cell = devm_nvmem_cell_get(priv->dev, name); in uniphier_u3hsphy_get_nvparam()
108 if (IS_ERR(cell)) in uniphier_u3hsphy_get_nvparam()
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
26 host-only mode.
[all …]
H A Dusb-xhci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/usb-xhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathias Nyman <mathias.nyman@intel.com>
13 - $ref: usb-hcd.yaml#
16 usb2-lpm-disable:
17 description: Indicates if we don't want to enable USB2 HW LPM
20 usb3-lpm-capable:
21 description: Determines if platform is USB3 LPM capable
[all …]
/linux/drivers/usb/core/
H A Dusb-acpi.c1 // SPDX-License-Identifier: GPL-2.0
3 * USB-ACPI glue code
19 * usb_acpi_power_manageable - check whether usb port has
24 * Return true if the port has acpi power resource and false if no.
33 if (port_handle) in usb_acpi_power_manageable()
40 #define UUID_USB_CONTROLLER_DSM "ce2ee385-00e6-48cb-9f05-2edb927c4899"
44 * usb_acpi_port_lpm_incapable - check if lpm should be disabled for a port.
48 * Some USB3 ports may not support USB3 link power management U1/U2 states
50 * if U1 and U2 states should be disabled. Evaluate _DSM with:
51 * Arg0: UUID = ce2ee385-00e6-48cb-9f05-2edb927c4899
[all …]

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