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/linux/drivers/usb/gadget/udc/
H A Drenesas_usb3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas USB3.0 Peripheral driver (USB gadget)
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
13 #include <linux/extcon-provider.h>
33 #define USB3_AXI_INT_STA 0x008
34 #define USB3_AXI_INT_ENA 0x00c
35 #define USB3_DMA_INT_STA 0x010
36 #define USB3_DMA_INT_ENA 0x014
37 #define USB3_DMA_CH0_CON(n) (0x030 + ((n) - 1) * 0x10) /* n = 1 to 4 */
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/linux/drivers/phy/broadcom/
H A Dphy-bcm-ns-usb3.c1 // SPDX-License-Identifier: GPL-2.0-only
26 #define BCM_NS_USB3_PHY_BASE_ADDR_REG 0x1f
27 #define BCM_NS_USB3_PHY_PLL30_BLOCK 0x8000
28 #define BCM_NS_USB3_PHY_TX_PMD_BLOCK 0x8040
29 #define BCM_NS_USB3_PHY_PIPE_BLOCK 0x8060
32 #define BCM_NS_USB3_PLL_CONTROL 0x01
33 #define BCM_NS_USB3_PLLA_CONTROL0 0x0a
34 #define BCM_NS_USB3_PLLA_CONTROL1 0x0b
37 #define BCM_NS_USB3_TX_PMD_CONTROL1 0x01
40 #define BCM_NS_USB3_LFPS_CMP 0x02
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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-usb43dp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
19 - qcom,sar2130p-qmp-usb3-dp-phy
20 - qcom,sc7180-qmp-usb3-dp-phy
21 - qcom,sc7280-qmp-usb3-dp-phy
22 - qcom,sc8180x-qmp-usb3-dp-phy
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H A Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
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H A Dsocionext,uniphier-usb3ss-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-ssphy
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H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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H A Dsocionext,uniphier-usb3hs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
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H A Dbcm-ns-usb3-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/bcm-ns-usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 Known A0: BCM4707 rev 0
15 Known C0: BCM47094 rev 0
18 - Rafał Miłecki <rafal@milecki.pl>
23 - brcm,ns-ax-usb3-phy
24 - brcm,ns-bx-usb3-phy
30 usb3-dmp-syscon:
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H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dsocionext,uniphier-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/socionext,uniphier-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This regulator controls VBUS and belongs to USB3 glue layer. Before using
15 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17 # USB3 Controller
22 - socionext,uniphier-pro4-usb3-regulator
23 - socionext,uniphier-pro5-usb3-regulator
24 - socionext,uniphier-pxs2-usb3-regulator
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234-p3768-0000+p3767.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-bindings/input/gpio-keys.h>
6 #include "tegra234-p3767.dtsi"
17 stdout-path = "serial0:115200n8";
20 bus@0 {
22 compatible = "nvidia,tegra194-hsuart";
23 reset-names = "serial";
28 compatible = "nvidia,tegra194-hsuart";
29 reset-names = "serial";
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H A Dtegra234-p3740-0002+p3701-0008.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/sound/rt5640.h>
7 #include "tegra234-p3701-0008.dtsi"
11 compatible = "nvidia,p3740-0002+p3701-0008", "nvidia,p3701-0008", "nvidia,tegra234";
19 stdout-path = "serial0:115200n8";
22 bus@0 {
29 dai-format = "i2s";
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/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra194-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
18 const: nvidia,tegra194-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
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H A Dfsl,imx8qm-cdns3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/fsl,imx8qm-cdns3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Frank Li <Frank.Li@nxp.com>
15 const: fsl,imx8qm-usb3
19 - description: Register set for iMX USB3 Platform Control
21 "#address-cells":
24 "#size-cells":
31 - description: Standby clock. Used during ultra low power states.
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H A Dnvidia,tegra186-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
18 const: nvidia,tegra186-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
[all …]
H A Dnvidia,tegra124-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
20 - description: NVIDIA Tegra124
21 const: nvidia,tegra124-xusb
23 - description: NVIDIA Tegra132
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/linux/Documentation/devicetree/bindings/reset/
H A Dsocionext,uniphier-glue-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-reset
22 - socionext,uniphier-pro5-usb3-reset
23 - socionext,uniphier-pxs2-usb3-reset
24 - socionext,uniphier-ld20-usb3-reset
25 - socionext,uniphier-pxs3-usb3-reset
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/linux/fs/ufs/
H A Dutil.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 return &cpi->c_ubh; in UCPI_UBH()
23 return &spi->s_ubh; in USPI_UBH()
33 struct ufs_super_block_third *usb3) in ufs_get_fs_state() argument
35 switch (UFS_SB(sb)->s_flags & UFS_ST_MASK) { in ufs_get_fs_state()
37 if (fs32_to_cpu(sb, usb3->fs_postblformat) == UFS_42POSTBLFMT) in ufs_get_fs_state()
38 return fs32_to_cpu(sb, usb1->fs_u0.fs_sun.fs_state); in ufs_get_fs_state()
41 return fs32_to_cpu(sb, usb3->fs_un2.fs_sun.fs_state); in ufs_get_fs_state()
43 return fs32_to_cpu(sb, usb1->fs_u1.fs_sunx86.fs_state); in ufs_get_fs_state()
46 return fs32_to_cpu(sb, usb3->fs_un2.fs_44.fs_state); in ufs_get_fs_state()
[all …]
H A Dsuper.c1 // SPDX-License-Identifier: GPL-2.0-only
16 * Laboratoire MASI - Institut Blaise Pascal
25 * Big-endian to little-endian byte-swapping/bitmaps by
35 * Adrian Rodriguez (adrian@franklins-tower.rutgers.edu)
48 * Francois-Rene Rideau <fare@tunes.org>
52 * on code by Martin von Loewis <martin@mira.isdn.cs.tu-berlin.de>.
84 #include <linux/backing-dev.h>
101 struct ufs_sb_private_info *uspi = UFS_SB(sb)->s_uspi; in ufs_nfs_get_inode()
104 if (ino < UFS_ROOTINO || ino > (u64)uspi->s_ncg * uspi->s_ipg) in ufs_nfs_get_inode()
105 return ERR_PTR(-ESTALE); in ufs_nfs_get_inode()
[all …]
/linux/drivers/phy/tegra/
H A Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
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H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
22 #define HS_CURR_LEVEL_PAD_MASK 0x3f
24 #define HS_TERM_RANGE_ADJ_MASK 0xf
26 #define HS_SQUELCH_MASK 0x7
28 #define RPD_CTRL_SHIFT 0
29 #define RPD_CTRL_MASK 0x1f
32 #define XUSB_PADCTL_USB2_PAD_MUX 0x4
34 #define USB2_PORT_MASK 0x3
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/linux/Documentation/devicetree/bindings/soc/socionext/
H A Dsocionext,uniphier-dwc3-glue.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
15 USB3.0 component.
20 - enum:
21 - socionext,uniphier-pro4-dwc3-glue
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/linux/Documentation/devicetree/bindings/nvmem/
H A Dmediatek,efuse.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Andrew-CT Chen <andrew-ct.chen@mediatek.com>
15 - Lala Lin <lala.lin@mediatek.com>
18 - $ref: nvmem.yaml#
19 - $ref: nvmem-deprecated-cells.yaml#
23 pattern: "^efuse@[0-9a-f]+$"
27 - items:
28 - const: mediatek,mt8188-efuse
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/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-s922x-khadas-vim3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-g12b-s922x.dtsi"
11 #include "meson-khadas-vim3.dtsi"
12 #include "meson-g12b-khadas-vim3.dtsi"
19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
21 * an USB3.0 Type A connector and a M.2 Key M slot.
23 * the USB3.0 controller and the PCIe Controller, thus only
25 * If the MCU is configured to mux the PCIe/USB3.0 differential lines
27 * USB3.0 from the USB Complex and enable the PCIe controller.
[all …]

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