/linux/Documentation/devicetree/bindings/usb/ |
H A D | amlogic,meson-g12a-usb-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Neil Armstrong <neil.armstrong@linaro.org> 14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3 15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode 18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY. 20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP. 25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in [all …]
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H A D | fsl,usb2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/fsl,usb2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Frank Li <Frank.Li@nxp.com> 21 - enum: 22 - fsl-usb2-mph 23 - fsl-usb2-dr 24 - items: 25 - enum: [all …]
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H A D | nvidia,tegra210-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces 18 const: nvidia,tegra210-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers [all …]
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H A D | nvidia,tegra194-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces 18 const: nvidia,tegra194-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers [all …]
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H A D | nvidia,tegra234-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra234-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by 20 const: nvidia,tegra234-xusb 24 - description: xHCI host registers 25 - description: XUSB FPCI registers [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | socionext,uniphier-usb2-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Socionext UniPhier USB2 PHY 11 USB2 controller implemented on Socionext UniPhier SoCs. 12 Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3 13 controller doesn't include its own High-Speed PHY. This needs to specify 14 USB2 PHY instead of USB3 HS-PHY. 17 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> [all …]
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H A D | samsung,usb2-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/samsung,usb2-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 - Marek Szyprowski <m.szyprowski@samsung.com> 12 - Sylwester Nawrocki <s.nawrocki@samsung.com> 18 0 - USB device ("device"), 19 1 - USB host ("host"), 20 2 - HSIC0 ("hsic0"), [all …]
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H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | amlogic,meson8b-usb2-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/amlogic,meson8b-usb2-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY 10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com> 15 - items: 16 - enum: 17 - amlogic,meson8-usb2-phy 18 - amlogic,meson8b-usb2-phy [all …]
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H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | ti,omap-usb2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/ti,omap-usb2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: OMAP USB2 PHY 10 - Kishon Vijay Abraham I <kishon@ti.com> 11 - Roger Quadros <rogerq@kernel.org> 16 - items: 17 - enum: 18 - ti,dra7x-usb2 [all …]
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H A D | phy-hisi-inno-usb2.txt | 1 Device tree bindings for HiSilicon INNO USB2 PHY 4 - compatible: Should be one of the following strings: 5 "hisilicon,inno-usb2-phy", 6 "hisilicon,hi3798cv200-usb2-phy". 7 - reg: Should be the address space for PHY configuration register in peripheral 9 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device 11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset 13 - #address-cells: Must be 1. 14 - #size-cells: Must be 0. 16 The INNO USB2 PHY device should be a child node of peripheral controller that [all …]
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/linux/drivers/phy/tegra/ |
H A D | xusb-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved. 21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0) 33 #define USB2_PORT_SHIFT(x) ((x) * 2) 58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \ 59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \ 65 #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3) 80 #define USB2_OTG_PD_DR BIT(2) 140 #define UTMI_LS SPEED(2) 154 #define FAKE_USBOP_EN BIT(2) [all …]
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H A D | xusb-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only 86 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL2(x) ((x) < 2 ? 0x078 + (x) * 4 : \ 92 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL5(x) ((x) < 2 ? 0x090 + (x) * 4 : \ 96 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(x) ((x) < 2 ? 0x098 + (x) * 4 : \ 128 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2) 134 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 2 158 #define XUSB_PADCTL_HSIC_PAD_CTL1_PD_TX (1 << 2) 229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable() 231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable() 251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable() [all …]
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/linux/Documentation/admin-guide/media/ |
H A D | dvb-usb-dw2102-cardlist.rst | 1 .. SPDX-License-Identifier: GPL-2.0 3 dvb-usb-dw2102 cards list 8 .. flat-table:: 9 :header-rows: 1 11 :stub-columns: 0 13 * - Card name 14 - USB IDs 15 * - DVBWorld DVB-C 3101 USB2.0 16 - 04b4:3101 17 * - DVBWorld DVB-S 2101 USB2.0 [all …]
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/linux/drivers/usb/host/ |
H A D | fsl-mph-dr-of.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Setup platform devices needed by the Freescale multi-port host 4 * and/or dual-role USB controller modules based on the description 17 #include <linux/dma-mapping.h> 28 .drivers = { "fsl-ehci", NULL, NULL, }, 33 .drivers = { "fsl-usb2-otg", "fsl-ehci", "fsl-usb2-udc", }, 38 .drivers = { "fsl-usb2-udc", NULL, NULL, }, 84 const struct resource *res = ofdev->resource; in fsl_usb2_device_register() 85 unsigned int num = ofdev->num_resources; in fsl_usb2_device_register() 90 retval = -ENOMEM; in fsl_usb2_device_register() [all …]
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/linux/Documentation/devicetree/bindings/clock/ |
H A D | renesas,rcar-usb2-clock-sel.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas R-Car USB 2.0 clock selector 10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 19 Case 1: An external clock connects to R-Car SoC 20 +----------+ +--- R-Car ---------------------+ 21 |External |---|USB_EXTAL ---> all usb channels| 23 +----------+ +-------------------------------+ [all …]
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/linux/drivers/media/usb/dvb-usb/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 8 USB1.1 and USB2.0 DVB devices. 11 <file:Documentation/driver-api/media/drivers/dvb-usb.rst>. 19 bool "Enable extended debug support for all DVB-USB devices" 22 Say Y if you want to enable debugging. See modinfo dvb-usb (and the 28 tristate "AVerMedia AverTV DVB-T USB 2.0 (A800)" 34 Say Y here to support the AVerMedia AverTV DVB-T USB 2.0 (A800) receiver. 37 tristate "Afatech AF9005 DVB-T USB1.1 support" 42 Say Y here to support the Afatech AF9005 based DVB-T USB1.1 receiver 53 tristate "Azurewave DVB-S/S2 USB2.0 AZ6027 support" [all …]
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/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra124-nyan.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/input/input.h> 3 #include <dt-bindings/thermal/thermal.h> 14 stdout-path = "serial0:115200n8"; 19 * version 1.4.2) warn about this node containing a reg property, but 20 * missing a unit-address. However, the bootloader on these Chromebook 22 * Adding the unit-address causes the bootloader to create a /memory 24 * turn leads the kernel to believe that the device has 2 GiB of 34 /delete-node/ memory@80000000; 40 vdd-supply = <&vdd_3v3_hdmi>; [all …]
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/linux/arch/arm/boot/dts/broadcom/ |
H A D | bcm47081-tplink-archer-c5-v2.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 6 /dts-v1/; 11 compatible = "tplink,archer-c5-v2", "brcm,bcm47081", "brcm,bcm4708"; 12 model = "TP-LINK Archer C5 V2"; 24 compatible = "gpio-leds"; 26 led-2ghz { 27 label = "bcm53xx:green:2ghz"; 31 led-lan { 36 led-usb2-port1 { 37 label = "bcm53xx:green:usb2-port1"; [all …]
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H A D | bcm47094-dlink-dir-890l.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 3 * Device tree for D-Link DIR-890L 4 * D-Link calls this board "WRGAC36" 5 * this router has the same looks and form factor as D-Link DIR-885L. 7 * Some differences from DIR-885L include a separate USB2 port, separate LEDs 8 * for USB2 and USB3, a separate VCC supply for the USB2 slot and no 13 * Based on the device tree for DIR-885L 18 /dts-v1/; 21 #include "bcm5301x-nand-cs0-bch1.dtsi" 24 compatible = "dlink,dir-890l", "brcm,bcm47094", "brcm,bcm4708"; [all …]
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/linux/arch/powerpc/boot/dts/fsl/ |
H A D | mpc8536si-post.dtsi | 20 * Foundation, either version 2 of that License or (at your option) any 36 #address-cells = <2>; 37 #size-cells = <1>; 38 compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus"; 39 interrupts = <19 2 0 0>; 44 compatible = "fsl,mpc8540-pci"; 47 bus-range = <0 0xff>; 48 #interrupt-cells = <1>; 49 #size-cells = <2>; 50 #address-cells = <3>; [all …]
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/linux/arch/arm64/boot/dts/nvidia/ |
H A D | tegra186-p3509-0000+p3636-0001.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/linux-event-codes.h> 5 #include <dt-bindings/input/gpio-keys.h> 6 #include <dt-bindings/mfd/max77620.h> 12 compatible = "nvidia,p3509-0000+p3636-0001", "nvidia,tegra186"; 30 stdout-path = "serial0:115200n8"; 41 phy-reset-gpios = <&gpio_aon TEGRA186_AON_GPIO(AA, 6) GPIO_ACTIVE_LOW>; 42 phy-handle = <&phy>; 43 phy-mode = "rgmii-id"; [all …]
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