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/freebsd/sys/contrib/device-tree/Bindings/edac/
H A Dsocfpga-eccmgr.txt1 Altera SoCFPGA ECC Manager
2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
3 The ECC Manager counts and corrects single bit errors and counts/handles
6 Cyclone5 and Arria5 ECC Manager
8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
15 L2 Cache ECC
17 - compatible : Should be "altr,socfpga-l2-ecc"
[all …]
H A Daltr,socfpga-ecc-manager.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/edac/altr,socfpga-ecc-manager.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Altera SoCFPGA ECC Manager
11 - Matthew Gerlach <matthew.gerlach@altera.com>
15 ECC Manager for the Cyclone5, Arria5, Arria10, Stratix10, and Agilex chip
22 - items:
23 - const: altr,socfpga-s10-ecc-manager
24 - const: altr,socfpga-a10-ecc-manager
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
H A Dsocfpga_stratix10_socdk_nand.dts1 // SPDX-License-Identifier: GPL-2.0-only
10 compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
25 led-hps0 {
30 led-hps1 {
35 led-hps2 {
47 ref_033v: regulator-v-ref {
48 compatible = "regulator-fixed";
49 regulator-name = "0.33V";
[all …]
H A Dsocfpga_stratix10_socdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
10 compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
25 led-hps0 {
30 led-hps1 {
35 led-hps2 {
47 ref_033v: regulator-v-ref {
48 compatible = "regulator-fixed";
49 regulator-name = "0.33V";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91-kizboxmini-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board
5 * Copyright (C) 2014-2018 Overkiz SAS
16 stdout-path = &dbgu;
25 clock-frequency = <12000000>;
29 clock-frequency = <32768>;
38 compatible = "gpio-keys";
40 key-prog {
44 wakeup-source;
47 key-reset {
[all …]
H A Dat91-wb45n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-wb45n.dtsi - Device Tree file for WB45NBT board
12 model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)";
17 stdout-path = "serial0:115200n8";
26 atheros,board-id = "SD32";
31 compatible = "atmel,sama5d3-rstc";
35 atmel,wakeup-mode = "low";
39 clock-frequency = <32768>;
43 clock-frequency = <12000000>;
48 nand_controller: nand-controller {
[all …]
H A Dat91-lmu5000.dts1 // SPDX-License-Identifier: GPL-2.0-only
8 /dts-v1/;
24 #address-cells = <1>;
25 #size-cells = <1>;
29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <18432000>;
42 nand_controller: nand-controller {
43 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
44 pinctrl-names = "default";
49 rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
[all …]
H A Dat91-sama5d3_ksz9477_evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 /dts-v1/;
9 model = "EVB-KSZ9477";
10 compatible = "microchip,sama5d3-ksz9477-evb", "atmel,sama5d36",
14 stdout-pat
[all...]
H A Dat91-som60.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-som60.dtsi - Device Tree file for the SOM60 module
16 stdout-path = &dbgu;
25 clock-frequency = <32768>;
29 clock-frequency = <12000000>;
107 bus-width = <8>;
115 bus-width = <4>;
120 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
124 atmel,use-dma-rx;
125 atmel,use-dma-tx;
[all …]
H A Dat91-wb50n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-wb50n.dtsi - Device Tree include file for wb50n cpu module
12 model = "Laird Workgroup Bridge 50N - Atmel SAMA5D";
17 stdout-path = "serial0:115200n8";
38 clock-frequency = <32768>;
42 clock-frequency = <12000000>;
46 atmel,osc-bypass;
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
52 cd-gpios = <&pioC 26 GPIO_ACTIVE_LOW>;
[all …]
H A Dat91sam9n12ek.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board
8 /dts-v1/;
12 model = "Atmel AT91SAM9N12-EK";
17 stdout-path = "serial0:115200n8";
26 clock-frequency = <32768>;
30 clock-frequency = <16000000>;
46 compatible = "atmel,tcb-timer";
51 compatible = "atmel,tcb-timer";
63 clock-names = "mclk";
[all …]
H A Dat91-sam9x60_curiosity.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sam9x60_curiosity.dts - Device Tree file for Microchip SAM9X60 Curiosity board
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
15 compatible = "microchip,sam9x60-curiosity", "microchip,sam9x60", "atmel,at91sam9";
24 stdout-path = "serial0:115200n8";
33 clock-frequency = <32768>;
37 clock-frequency = <24000000>;
41 gpio-keys {
42 compatible = "gpio-keys";
[all …]
H A Dat91-sama5d3_eds.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * at91-sama5d3_eds.dts - Device Tree file for the SAMA5D3 Ethernet
10 /dts-v1/;
15 compatible = "microchip,sama5d3-eds", "atmel,sama5d36",
19 stdout-path = "serial0:115200n8";
22 gpio-keys {
23 compatible = "gpio-keys";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_key_gpio>;
28 button-3 {
[all …]
H A Dethernut5.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * ethernut5.dts - Device Tree file for Ethernut 5 board
7 /dts-v1/;
24 clock-frequency = <32768>;
28 clock-frequency = <18432000>;
40 compatible = "atmel,tcb-timer";
45 compatible = "atmel,tcb-timer";
59 phy-mode = "rmii";
64 atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
72 nand_controller: nand-controller {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-k2l-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2l.dtsi"
13 compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
[all …]
H A Dkeystone-k2e-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2e.dtsi"
13 compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
[all …]
H A Dkeystone-k2hk-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2hk.dtsi"
13 compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddm8148-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
9 compatible = "ti,dm8148-evm", "ti,dm8148", "ti,dm814";
18 compatible = "regulator-fixed";
19 regulator-name = "vmmcsd_fixed";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
26 phy-handle = <&ethphy0>;
27 phy-mode = "rgmii-id";
[all …]
H A Ddra62x-j5eco-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
9 compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148", "ti,dm814";
18 compatible = "regulator-fixed";
19 regulator-name = "vmmcsd_fixed";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
26 phy-handle = <&ethphy0>;
27 phy-mode = "rgmii-id";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-385-atl-x530.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 (x530/AT-GS980MX)
9 /dts-v1/;
10 #include "armada-385.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
15 model = "x530/AT-GS980MX";
19 stdout-path = "serial1:115200n8";
32 internal-regs {
34 pinctrl-names = "default";
35 pinctrl-0 = <&i2c0_pins>;
[all …]
H A Darmada-385-linksys.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include "armada-385.dtsi"
18 stdout-path = "serial0:115200n8";
34 usb3_1_phy: usb3_1-phy {
35 compatible = "usb-nop-xcei
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
[all …]

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