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/linux/drivers/usb/common/
H A Dulpi.c1 // SPDX-License-Identifier: GPL-2.0
3 * ulpi.c - USB ULPI PHY bus
10 #include <linux/ulpi/interface.h>
11 #include <linux/ulpi/driver.h>
12 #include <linux/ulpi/regs.h>
19 #include <linux/clk/clk-conf.h>
21 /* -------------------------------------------------------------------------- */
23 int ulpi_read(struct ulpi *ulpi, u8 addr) in ulpi_read() argument
25 return ulpi->ops->read(ulpi->dev.parent, addr); in ulpi_read()
29 int ulpi_write(struct ulpi *ulpi, u8 addr, u8 val) in ulpi_write() argument
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-usb-hsic.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/ulpi/driver.h>
7 #include <linux/ulpi/regs.h>
10 #include <linux/pinctrl/pinctrl-state.h>
14 #define ULPI_HSIC_CFG 0x30
15 #define ULPI_HSIC_IO_CAL 0x33
18 struct ulpi *ulpi; member
29 struct ulpi *ulpi = uphy->ulpi; in qcom_usb_hsic_phy_power_on() local
33 ret = clk_prepare_enable(uphy->phy_clk); in qcom_usb_hsic_phy_power_on()
37 ret = clk_prepare_enable(uphy->cal_clk); in qcom_usb_hsic_phy_power_on()
[all …]
H A Dphy-qcom-usb-hs.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/ulpi/driver.h>
7 #include <linux/ulpi/regs.h>
16 #define ULPI_PWR_CLK_MNG_REG 0x88
17 # define ULPI_PWR_OTG_COMP_DISABLE BIT(0)
19 #define ULPI_MISC_A 0x96
21 # define ULPI_MISC_A_VBUSVLDEXT BIT(0)
30 struct ulpi *ulpi; member
49 if (!uphy->vbus_edev) { in qcom_usb_hs_phy_set_mode()
50 u8 val = 0; in qcom_usb_hs_phy_set_mode()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
124 controllers on Qualcomm chips. This driver supports the high-speed
133 Enable support for the USB high-speed eUSB2 repeater on Qualcomm
174 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
177 Support for the USB high-speed ULPI compliant phy on Qualcomm
185 Enable support for the USB high-speed SNPS Femto phy on Qualcomm
191 tristate "Qualcomm USB HSIC ULPI PHY module"
195 Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
198 tristate "Qualcomm 28nm High-Speed PHY"
[all …]
/linux/drivers/usb/dwc3/
H A Dulpi.c1 // SPDX-License-Identifier: GPL-2.0
3 * ulpi.c - DesignWare USB3 Controller's ULPI PHY interface
12 #include <linux/ulpi/regs.h>
36 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); in dwc3_ulpi_busyloop()
40 while (count--) { in dwc3_ulpi_busyloop()
42 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); in dwc3_ulpi_busyloop()
44 return 0; in dwc3_ulpi_busyloop()
48 return -ETIMEDOUT; in dwc3_ulpi_busyloop()
58 dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg); in dwc3_ulpi_read()
64 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); in dwc3_ulpi_read()
[all …]
/linux/drivers/phy/ti/
H A Dphy-tusb1210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tusb1210.c - TUSB1210 USB ULPI PHY driver
12 #include <linux/ulpi/driver.h>
13 #include <linux/ulpi/regs.h>
20 #define TI_VENDOR_ID 0x0451
21 #define TI_DEVICE_TUSB1210 0x1507
22 #define TI_DEVICE_TUSB1211 0x1508
24 #define TUSB1211_POWER_CONTROL 0x3d
25 #define TUSB1211_POWER_CONTROL_SET 0x3e
26 #define TUSB1211_POWER_CONTROL_CLEAR 0x3f
[all …]
/linux/drivers/phy/tegra/
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? 15 : 0)
22 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
24 #define FUSE_SKU_CALIB_HS_IREF_CAP_MASK 0x3
26 #define FUSE_SKU_CALIB_HS_SQUELCH_LEVEL_MASK 0x3
28 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
30 #define XUSB_PADCTL_USB2_PORT_CAP 0x008
32 #define XUSB_PADCTL_USB2_PORT_CAP_PORT_CAP_MASK 0x3
33 #define XUSB_PADCTL_USB2_PORT_CAP_DISABLED 0x0
34 #define XUSB_PADCTL_USB2_PORT_CAP_HOST 0x1
[all …]
H A Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
[all …]
/linux/include/linux/mfd/
H A Dmotorola-cpcap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2007-2009 Motorola, Inc.
17 #define CPCAP_VENDOR_ST 0
21 #define CPCAP_REVISION_MINOR(r) ((r) & 0xf)
23 #define CPCAP_REVISION_1_0 0x08
24 #define CPCAP_REVISION_1_1 0x09
25 #define CPCAP_REVISION_2_0 0x10
26 #define CPCAP_REVISION_2_1 0x11
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
30 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra20-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
19 - nvidia,tegra124-usb-phy
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dmotorola,cpcap-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/motorola,cpcap-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
15 - motorola,cpcap-usb-phy
16 - motorola,mapphone-cpcap-usb-phy
18 '#phy-cells':
19 const: 0
24 - description: id_ground interrupt
[all …]
H A Dqcom,usb-hs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 - qcom,usb-hs-phy-apq8064
18 - qcom,usb-hs-phy-msm8660
19 - qcom,usb-hs-phy-msm8960
25 reset-names:
34 reset-names:
[all …]
/linux/arch/powerpc/platforms/83xx/
H A Dusb_831x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
28 int ret = 0; in mpc831x_usb_cfg()
33 np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr"); in mpc831x_usb_cfg()
35 return -ENODEV; in mpc831x_usb_cfg()
39 immap = ioremap(get_immrbase(), 0x1000); in mpc831x_usb_cfg()
42 return -ENOMEM; in mpc831x_usb_cfg()
47 if (immr_node && (of_device_is_compatible(immr_node, "fsl,mpc8315-immr") || in mpc831x_usb_cfg()
48 of_device_is_compatible(immr_node, "fsl,mpc8308-immr"))) in mpc831x_usb_cfg()
57 /* Configure pin mux for ULPI. There is no pin mux for UTMI */ in mpc831x_usb_cfg()
58 if (prop && !strcmp(prop, "ulpi")) { in mpc831x_usb_cfg()
[all …]
H A Dusb_837x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 int ret = 0; in mpc837x_usb_cfg()
27 np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr"); in mpc837x_usb_cfg()
30 return -ENODEV; in mpc837x_usb_cfg()
34 if (!prop || (strcmp(prop, "ulpi") && strcmp(prop, "serial"))) { in mpc837x_usb_cfg()
37 return -EINVAL; in mpc837x_usb_cfg()
41 immap = ioremap(get_immrbase(), 0x1000); in mpc837x_usb_cfg()
44 return -ENOMEM; in mpc837x_usb_cfg()
51 /* Configure pin mux for ULPI/serial */ in mpc837x_usb_cfg()
/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-apalis.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
11 * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A
15 reg = <0x0 0x80000000 0x0 0x80000000>;
20 avddio-pex-supply = <&reg_1v05_vdd>;
21 avdd-pex-pll-supply = <&reg_1v05_vdd>;
22 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
23 dvddio-pex-supply = <&reg_1v05_vdd>;
24 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
[all …]
H A Dtegra124-apalis-v1.2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2016-2018 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
15 reg = <0x0 0x80000000 0x0 0x80000000>;
21 avddio-pex-supply = <&reg_1v05_vdd>;
22 avdd-pex-pll-supply = <&reg_1v05_vdd>;
23 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
24 dvddio-pex-supply = <&reg_1v05_vdd>;
25 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
26 hvdd-pex-supply = <&reg_module_3v3>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Dasp834x-redboot.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 compatible = "analogue-and-micro,asp8347e";
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
27 PowerPC,8347@0 {
29 reg = <0x0>;
30 d-cache-line-size = <32>;
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8536ds.dtsi2 * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
[all …]
H A Dp1020utm-pc.dtsi2 * P1020 UTM-PC Device Tree Source stub (no addresses or top-level ranges)
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x2000000>;
41 bank-width = <2>;
42 device-width = <1>;
44 partition@0 {
46 reg = <0x0 0x00040000>;
[all …]
/linux/drivers/usb/phy/
H A Dphy-tegra-usb.c1 // SPDX-License-Identifier: GPL-2.0
30 #include <linux/usb/ulpi.h>
32 #define ULPI_VIEWPORT 0x170
35 #define TEGRA_USB_PORTSC1 0x184
36 #define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
40 #define TEGRA_USB_HOSTPC1_DEVLC 0x1b4
41 #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29)
47 #define USB_SUSP_CTRL 0x400
58 #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
60 #define USB_PHY_VBUS_SENSORS 0x404
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx27-phytec-phycard-s-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
7 /dts-v1/;
12 compatible = "phytec,imx27-pca100", "fsl,imx27";
16 reg = <0xa0000000 0x08000000>; /* 128MB */
20 compatible = "usb-nop-xceiv";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_usbotgphy>;
23 reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
24 #phy-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
22 "ohci-phy-6pin-dpdm",
[all …]
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra114.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
16 #include "pinctrl-tegra.h"
24 #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
194 /* All non-GPIO pins follow */
198 /* Non-GPIO pins */
199 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
1525 FUNCTION(ulpi),
1538 #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1539 #define PINGROUP_REG_A 0x3000 /* bank 1 */
[all …]

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