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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dnvidia,tegra20-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
19 - nvidia,tegra124-usb-phy
[all …]
H A Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
34 --------------------
35 - compatible: Must be:
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dqcom,usb-hs-phy.txt5 - compatible:
8 Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the
11 "qcom,usb-hs-phy-apq8064"
12 "qcom,usb-hs-phy-msm8916"
13 "qcom,usb-hs-phy-msm8974"
15 - #phy-cells:
18 Definition: Should contain 0
20 - clocks:
22 Value type: <prop-encoded-array>
26 - clock-names:
[all …]
H A Dqcom,usb-hs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 - qcom,usb-hs-phy-apq8064
18 - qcom,usb-hs-phy-msm8660
19 - qcom,usb-hs-phy-msm8960
25 reset-names:
34 reset-names:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dfsl-usb.txt9 - compatible : Should be "fsl-usb2-mph" for multi port host USB
10 controllers, or "fsl-usb2-dr" for dual role USB controllers
11 or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121.
13 also be mentioned (for eg. fsl-usb2-dr-v2.2 for bsc9132).
14 - phy_type : For multi port host USB controllers, should be one of
15 "ulpi", or "serial". For dual role USB controllers, should be
16 one of "ulpi", "utmi", "utmi_wide", or "serial".
17 - reg : Offset and length of the register set for the device
18 - port0 : boolean; if defined, indicates port0 is connected for
19 fsl-usb2-mph compatible controllers. Either this property or
[all …]
H A Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
35 - const: snps,dwc3
[all …]
H A Ddwc3.txt3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra124-apalis.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
11 * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A
15 reg = <0x0 0x8000000
[all...]
H A Dtegra124-apalis-v1.2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2016-2018 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
15 reg = <0x0 0x80000000 0x0 0x8000000
[all...]
H A Dtegra20-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 memory@0 {
17 reg = <0x00000000 0x10000000>;
22 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
23 nvidia,hpd-gpio =
25 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
26 vdd-supply = <&reg_3v3_avdd_hdmi>;
31 lan-reset-n-hog {
32 gpio-hog;
34 output-high;
[all …]
H A Dtegra124-nyan-blaze.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra124-nyan.dtsi"
6 #include "tegra124-nyan-blaze-emc.dtsi"
10 compatible = "google,nyan-blaze-rev10", "google,nyan-blaze-rev9",
11 "google,nyan-blaze-rev8", "google,nyan-blaze-rev7",
12 "google,nyan-blaze-rev6", "google,nyan-blaze-rev5",
13 "google,nyan-blaze-rev4", "google,nyan-blaze-rev3",
14 "google,nyan-blaze-rev2", "google,nyan-blaze-rev1",
15 "google,nyan-blaze-rev0", "google,nyan-blaze",
[all …]
/freebsd/sys/arm/nvidia/
H A Dtegra_pinmux.c1 /*-
49 #define TEGRA_MUX_FUNCTION_MASK 0x03
50 #define TEGRA_MUX_FUNCTION_SHIFT 0
51 #define TEGRA_MUX_PUPD_MASK 0x03
64 #define TEGRA_GRP_DRV_TYPE_MASK 0x03
66 #define TEGRA_GRP_DRV_DRVDN_SLWR_MASK 0x03
68 #define TEGRA_GRP_DRV_DRVUP_SLWF_MASK 0x03
78 {"nvidia,tegra124-pinmux", 1},
79 {NULL, 0},
109 {"nvidia,enable-input", PROP_ID_ENABLE_INPUT},
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dasp834x-redboot.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 compatible = "analogue-and-micro,asp8347e";
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
27 PowerPC,8347@0 {
29 reg = <0x0>;
30 d-cache-line-size = <32>;
[all …]
H A Dmpc834x_mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
29 PowerPC,8349@0 {
31 reg = <0x0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8536ds.dtsi2 * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
[all …]
H A Dp1020utm-pc.dtsi2 * P1020 UTM-PC Device Tree Source stub (no addresses or top-level ranges)
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x2000000>;
41 bank-width = <2>;
42 device-width = <1>;
44 partition@0 {
46 reg = <0x0 0x00040000>;
[all …]
H A Dp1020mbg-pc.dtsi2 * P1020 MBG-PC Device Tree Source stub (no addresses or top-level ranges)
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x4000000>;
41 bank-width = <2>;
42 device-width = <1>;
44 partition@0 {
46 reg = <0x0 0x00020000>;
[all …]
H A Dp1022rdk.dts2 * P1022 RDK 32-bit Physical Address Map Device Tree Source
35 /include/ "p1022si-pre.dtsi"
50 ranges = <0x0 0x0 0xffe00000 0x100000>;
55 reg = <0x1a>;
56 /* MCLK source is a stand-alone oscillator */
57 clock-frequency = <12288000>;
61 reg = <0x6
[all...]
H A Dp1020rdb-pc.dtsi2 * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x1000000>;
41 bank-width = <2>;
42 device-width = <1>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
[all …]
H A Dp1020rdb.dtsi2 * P1020 RDB Device Tree Source stub (no addresses or top-level ranges)
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x1000000>;
41 bank-width = <2>;
42 device-width = <1>;
44 partition@0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx27-phytec-phycard-s-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
7 /dts-v1/;
12 compatible = "phytec,imx27-pca100", "fsl,imx27";
16 reg = <0xa0000000 0x08000000>; /* 128MB */
20 compatible = "usb-nop-xceiv";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_usbotgphy>;
23 reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
24 #phy-cells = <0>;
[all …]
H A Dimx27-eukrea-cpuimx27.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
15 reg = <0xa0000000 0x04000000>;
18 clk14745600: clk-uart {
19 compatible = "fixed-cloc
[all...]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Domap-usb-host.txt5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
22 "ohci-phy-6pin-dpdm",
[all …]
/freebsd/sys/arm/ti/usb/
H A Domap_ehci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
63 #define OMAP_USBHOST_HCCAPBASE 0x0000
64 #define OMAP_USBHOST_HCSPARAMS 0x0004
65 #define OMAP_USBHOST_HCCPARAMS 0x0008
66 #define OMAP_USBHOST_USBCMD 0x0010
67 #define OMAP_USBHOST_USBSTS 0x0014
68 #define OMAP_USBHOST_USBINTR 0x0018
69 #define OMAP_USBHOST_FRINDEX 0x001C
70 #define OMAP_USBHOST_CTRLDSSEGMENT 0x0020
[all …]

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