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12

/linux/Documentation/devicetree/bindings/pinctrl/
H A Dcanaan,k230-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k230-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ze Huang <18771902331@163.com>
13 The Canaan Kendryte K230 platform includes 64 IO pins, each capable of
15 performed on a per-pin basis.
19 const: canaan,k230-pinctrl
25 '-pins$':
33 '-cfg$':
[all …]
/linux/arch/arm/boot/dts/hisilicon/
H A Dhi3620-hi4511.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013 Linaro Ltd.
7 /dts-v1/;
13 compatible = "hisilicon,hi3620-hi4511";
17 stdout-path = "serial0:115200n8";
25 amba-bus {
31 pinctrl-names = "default", "sleep";
32 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
33 pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>;
38 pinctrl-names = "default", "sleep";
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhikey970-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/pinctrl/hisi.h>
10 range: gpio-range {
11 #pinctrl-single,gpio-range-cells = <3>;
15 compatible = "pinctrl-single";
17 #pinctrl-cells = <1>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
21 /* pin base, nr pins & gpio function */
[all …]
H A Dhikey960-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/hisi.h>
12 range: gpio-range {
13 #pinctrl-single,gpio-range-cells = <3>;
17 compatible = "pinctrl-single";
19 #pinctrl-cells = <1>;
20 #gpio-range-cells = <0x3>;
21 pinctrl-single,register-width = <0x20>;
22 pinctrl-single,function-mask = <0x7>;
23 /* pin base, nr pins & gpio function */
[all …]
H A Dhikey-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/pinctrl/hisi.h>
11 pinctrl-names = "default";
12 pinctrl-0 = <
20 boot_sel_pmx_func: boot-sel-pins {
21 pinctrl-single,pins = <
26 emmc_pmx_func: emmc-pins {
27 pinctrl-single,pins = <
41 sd_pmx_func: sd-pins {
42 pinctrl-single,pins = <
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-dhcom-drc02.dts1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2
7 * DHCOR PCB number: 578-200 or newer
8 * DHCOM PCB number: 579-200 or newer
9 * DRC02 PCB number: 568-100 or newer (2nd ethernet by SoM)
11 /dts-v1/;
13 #include "imx6ull-dhcom-som.dtsi"
14 #include "imx6ull-dhcom-som-cfg-sdcard.dtsi"
18 compatible = "dh,imx6ull-dhcom-drc02", "dh,imx6ull-dhcom-som",
19 "dh,imx6ull-dhcor-som", "fsl,imx6ull";
[all …]
H A Dimx6ul-14x14-evk.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/media/video-interfaces.h>
9 stdout-path = &uart1;
17 backlight_display: backlight-display {
18 compatible = "pwm-backlight";
20 brightness-levels = <0 4 8 16 32 64 128 255>;
21 default-brightness-level = <6>;
26 reg_sd1_vmmc: regulator-sd1-vmmc {
27 compatible = "regulator-fixed";
28 regulator-name = "VSD_3V3";
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-ocelot.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Author: <alexandre.belloni@free-electrons.com>
21 #include <linux/pinctrl/pinconf-generic.h>
324 [FUNC_UART2] = "uart2",
477 SERVAL_P(13, SFP, UART2, TWI_SCL_M);
478 SERVAL_P(14, SFP, UART2, TWI_SCL_M);
558 OCELOT_P(12, UART2, TWI_SCL_M, SFP);
559 OCELOT_P(13, UART2, TWI_SCL_M, SFP);
632 JAGUAR2_P(24, UART2, NONE);
633 JAGUAR2_P(25, UART2, SI);
[all …]
H A Dpinctrl-ingenic.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <linux/pinctrl/pinconf-generic.h>
177 (!(enabled_socs & GENMASK(version - 1, 0)) in is_soc_or_above()
178 || jzpc->info->version >= version); in is_soc_or_above()
224 INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1),
225 INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1),
226 INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1),
227 INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1),
228 INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1),
229 INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1),
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
16 stdout-path = &uart2;
19 backlight_lvds: backlight-lvds {
20 compatible = "pwm-backlight";
22 brightness-levels = <0 100>;
23 num-interpolated-steps = <100>;
24 default-brightness-level = <100>;
[all …]
H A Dimx8mn-beacon-baseboard.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 dmic_codec: dmic-codec {
8 compatible = "dmic-codec";
9 num-channels = <1>;
10 #sound-dai-cells = <0>;
14 compatible = "gpio-leds";
16 led-0 {
19 default-state = "off";
22 led-1 {
25 default-state = "off";
[all …]
H A Dimx8mp-beacon-kit.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/usb/pd.h>
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
11 #include "imx8mp-beacon-som.dtsi"
15 compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp";
23 stdout-path = &uart2;
26 clk_xtal25: clock-xtal25 {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
[all …]
H A Dimx8mm-beacon-baseboard.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 dmic_codec: dmic-codec {
11 compatible = "dmic-codec";
12 num-channels = <1>;
13 #sound-dai-cells = <0>;
17 compatible = "gpio-leds";
22 default-state = "off";
28 default-state = "off";
34 default-state = "off";
[all …]
H A Dimx8mq-librem5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 Purism SPC
6 /dts-v1/;
8 #include "dt-bindings/input/input.h"
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include "dt-bindings/pwm/pwm.h"
12 #include "dt-bindings/usb/pd.h"
18 chassis-type = "handset";
20 backlight_dsi: backlight-dsi {
[all …]
H A Dimx8-apalis-v1.1.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include <dt-bindings/pwm/pwm.h>
10 stdout-path = &lpuart1;
15 compatible = "pwm-backlight";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_bkl_on>;
18 brightness-levels = <0 45 63 88 119 158 203 255>;
19 default-brightness-level = <4>;
20 enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */
21 /* TODO: hook-up to Apalis BKL1_PWM */
[all …]
/linux/arch/arm/mach-omap1/
H A Dmux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/arch/arm/mach-omap1/mux.c
7 * Copyright (C) 2003 - 2008 Nokia Corporation
15 #include <linux/soc/ti/omap1-io.h>
33 /* UART2 (COM_UART_GATING), conflicts with USB2 */
83 /* OMAP-1510 GPIO */
92 /* OMAP-1710 GPIO */
129 /* OMAP-1610 MMC2 */
141 /* OMAP-1610 External Trace Interface */
164 /* OMAP-1610 uWire */
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210-fascinate4g.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include "s5pv210-aries.dtsi"
9 model = "Samsung Galaxy S Fascinate 4G (SGH-T959P) based on S5PV210";
11 chassis-type = "handset";
14 stdout-path = &uart2;
17 gpio-keys {
18 compatible = "gpio-keys";
[all …]
H A Ds5pv210-aries.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
32 reserved-memory {
33 #address-cells = <1>;
34 #size-cells = <1>;
38 compatible = "shared-dma-pool";
39 no-map;
44 compatible = "shared-dma-pool";
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/interconnect/qcom,msm8996.h>
12 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
[all …]
H A Dsa8775p.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/interconnect/qcom,icc.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
11 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
12 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h>
[all …]
H A Dsc7280.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
11 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
13 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
14 #include <dt-bindings/clock/qcom,rpmh.h>
[all …]
/linux/arch/arm/mach-mv78xx0/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-mv78xx0/common.c
14 #include <linux/clk-provider.h>
16 #include <asm/hardware/cache-feroceon-l2.h>
19 #include <linux/platform_data/usb-ehci-orion.h>
20 #include <linux/platform_data/mtd-orion_nand.h>
23 #include <plat/addr-map.h>
25 #include "bridge-regs.h"
50 * HCLK tick rate is configured by DEV_D[7:5] pins. in get_hclk()
78 u32 cfg; in get_pclk_l2clk() local
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
9 #include "rk3399-op1.dtsi"
18 stdout-path = "serial2:115200n8";
27 * - Rails that only connect to the EC (or devices that the EC talks to)
29 * - Rails _are_ included if the rails go to the AP even if the AP
38 * - The EC controls the enable and the EC always enables a rail as
40 * - The rails are actually connected to each other by a jumper and
45 ppvar_sys: regulator-ppvar-sys {
[all …]
H A Drk3399-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
[all …]
/linux/drivers/pinctrl/nuvoton/
H A Dpinctrl-npcm8xx.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/pinctrl/pinconf-generic.h>
123 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_set()
125 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_set()
133 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_clr()
135 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_clr()
143 ioread32(bank->base + NPCM8XX_GP_N_DIN), in npcmgpio_dbg_show()
144 ioread32(bank->base + NPCM8XX_GP_N_DOUT), in npcmgpio_dbg_show()
145 ioread32(bank->base + NPCM8XX_GP_N_IEM), in npcmgpio_dbg_show()
146 ioread32(bank->base + NPCM8XX_GP_N_OE)); in npcmgpio_dbg_show()
[all …]

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