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/linux/Documentation/devicetree/bindings/serial/
H A Dmediatek,uart.yaml4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
26 - mediatek,mt2701-uart
27 - mediatek,mt2712-uart
28 - mediatek,mt6572-uart
29 - mediatek,mt6580-uart
30 - mediatek,mt6582-uart
31 - mediatek,mt6589-uart
[all …]
H A Dsamsung_uart.yaml7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
22 - apple,s5l-uart
23 - axis,artpec8-uart
24 - google,gs101-uart
25 - samsung,s3c6400-uart
26 - samsung,s5pv210-uart
27 - samsung,exynos4210-uart
28 - samsung,exynos5433-uart
29 - samsung,exynos850-uart
[all …]
H A Dsnps-dw-apb-uart.yaml4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
7 title: Synopsys DesignWare ABP UART
21 - const: renesas,rzn1-uart
22 - const: snps,dw-apb-uart
32 const: starfive,jh7110-uart
46 - const: renesas,r9a06g032-uart
47 - const: renesas,rzn1-uart
48 - const: snps,dw-apb-uart
50 - const: renesas,r9a06g032-uart
51 - const: renesas,rzn1-uart
[all …]
H A Damlogic,meson-uart.yaml5 $id: http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#
8 title: Amlogic Meson SoC UART Serial Interface
14 The Amlogic Meson SoC UART Serial Interface is present on a large range
28 - description: Always-on power domain UART controller
31 - amlogic,meson6-uart
32 - amlogic,meson8-uart
33 - amlogic,meson8b-uart
34 - amlogic,meson-gx-uart
35 - amlogic,meson-s4-uart
36 - amlogic,meson-a1-uart
[all …]
H A Dfsl-imx-uart.yaml4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
15 - const: fsl,imx1-uart
16 - const: fsl,imx21-uart
19 - fsl,imx25-uart
20 - fsl,imx27-uart
21 - fsl,imx31-uart
22 - fsl,imx35-uart
23 - fsl,imx50-uart
24 - fsl,imx51-uart
[all …]
H A D8250.yaml7 title: UART (Universal Asynchronous Receiver/Transmitter)
30 const: mrvl,mmp-uart
55 const: nxp,lpc1850-uart
66 const: spacemit,k1-uart
78 - spacemit,k1-uart
79 - nxp,lpc1850-uart
106 - const: intel,xscale-uart
107 - const: mrvl,pxa-uart
108 - const: nuvoton,wpcm450-uart
109 - const: nuvoton,npcm750-uart
[all …]
H A Dmarvell,armada-3700-uart.yaml4 $id: http://devicetree.org/schemas/serial/marvell,armada-3700-uart.yaml#
7 title: Marvell Armada-3700 UART
13 Marvell UART is a non standard UART used in some of Marvell EBU SoCs (e.g.
19 - marvell,armada-3700-uart
20 - marvell,armada-3700-uart-ext
28 UART reference clock used to derive the baud rate. If absent, only fixed
34 - description: UART sum interrupt
35 - description: UART TX interrupt
36 - description: UART RX interrupt
55 const: marvell,armada-3700-uart-ext
[all …]
H A Dbrcm,bcm7271-uart.yaml4 $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
16 The Broadcom UART is based on the basic 8250 UART but with
24 - brcm,bcm7271-uart
25 - brcm,bcm7278-uart
32 description: The UART register block and optionally the DMA register blocks.
35 - const: uart
37 - const: uart
54 description: The UART interrupt and optionally the DMA interrupt.
57 - const: uart
74 compatible = "brcm,bcm7271-uart";
[all …]
H A Dingenic,uart.yaml4 $id: http://devicetree.org/schemas/serial/ingenic,uart.yaml#
7 title: Ingenic SoCs UART controller
22 - ingenic,jz4740-uart
23 - ingenic,jz4750-uart
24 - ingenic,jz4760-uart
25 - ingenic,jz4780-uart
26 - ingenic,x1000-uart
29 - ingenic,jz4770-uart
30 - ingenic,jz4775-uart
31 - const: ingenic,jz4760-uart
[all …]
/linux/drivers/tty/serial/
H A Dmen_z135_uart.c3 * MEN 16z135 High Speed UART
132 * @uart: The UART port
136 static inline void men_z135_reg_set(struct men_z135_port *uart, in men_z135_reg_set() argument
139 struct uart_port *port = &uart->port; in men_z135_reg_set()
143 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_set()
149 spin_unlock_irqrestore(&uart->lock, flags); in men_z135_reg_set()
154 * @uart: The UART port
158 static void men_z135_reg_clr(struct men_z135_port *uart, in men_z135_reg_clr() argument
161 struct uart_port *port = &uart->port; in men_z135_reg_clr()
165 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_clr()
[all …]
H A Dtimbuart.c3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
55 struct timbuart_port *uart = in timbuart_start_tx() local
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
115 struct timbuart_port *uart = in timbuart_handle_tx_port() local
134 *ier |= uart->last_ier & TXFLAGS; in timbuart_handle_tx_port()
171 struct timbuart_port *uart = from_tasklet(uart, t, tasklet); in timbuart_tasklet() local
174 uart_port_lock(&uart->port); in timbuart_tasklet()
176 isr = ioread32(uart->port.membase + TIMBUART_ISR); in timbuart_tasklet()
177 dev_dbg(uart->port.dev, "%s ISR: %x\n", __func__, isr); in timbuart_tasklet()
[all …]
H A DKconfig26 This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have
37 Say Y here if you wish to use an AMBA PrimeCell UART as the system
53 This selects the ARM(R) AMBA(R) PrimeCell PL011 UART. If you have
65 Say Y here if you wish to use an AMBA PrimeCell UART as the system
145 Say Y here if you wish to use an on-chip UART on a Atmel
180 Say Y if you have an external 8250/16C550 UART. If unsure, say N.
196 Say Y here if you wish to use a Amlogic MesonX UART as the
237 Select the number of available UART ports for the Samsung S3C
268 tristate "NVIDIA Tegra Combined UART"
273 Support for the mailbox-based TCU (Tegra Combined UART) serial port.
[all …]
/linux/include/uapi/linux/
H A Dserial_core.h19 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
20 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
21 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
22 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
23 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
24 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */
25 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
29 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
30 #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
31 #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
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/linux/drivers/tty/serial/8250/
H A D8250_tegra.c46 struct tegra_uart *uart; in tegra_uart_probe() local
51 uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL); in tegra_uart_probe()
52 if (!uart) in tegra_uart_probe()
84 uart->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); in tegra_uart_probe()
85 if (IS_ERR(uart->rst)) in tegra_uart_probe()
86 return PTR_ERR(uart->rst); in tegra_uart_probe()
89 uart->clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
90 if (IS_ERR(uart->clk)) { in tegra_uart_probe()
95 ret = clk_prepare_enable(uart->clk); in tegra_uart_probe()
99 port->uartclk = clk_get_rate(uart->clk); in tegra_uart_probe()
[all …]
H A D8250_platform.c114 struct uart_8250_port *uart __free(kfree) = kzalloc(sizeof(*uart), GFP_KERNEL); in serial8250_probe_acpi()
115 if (!uart) in serial8250_probe_acpi()
124 uart->port.iobase = regs->start; in serial8250_probe_acpi()
127 uart->port.mapbase = regs->start; in serial8250_probe_acpi()
128 uart->port.mapsize = resource_size(regs); in serial8250_probe_acpi()
129 uart->port.flags = UPF_IOREMAP; in serial8250_probe_acpi()
136 uart->port.uartclk = 1843200; in serial8250_probe_acpi()
137 uart->port.type = PORT_16550A; in serial8250_probe_acpi()
138 uart->port.dev = &pdev->dev; in serial8250_probe_acpi()
139 uart->port.flags |= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF; in serial8250_probe_acpi()
[all …]
H A D8250_core.c238 * IIR bits on their UART, but it's specifically designed for in serial8250_backup_timeout()
239 * the "Diva" UART used on the management processor on many HP in serial8250_backup_timeout()
408 * Check whether an invalid uart number has been specified, and in univ8250_console_setup()
452 * console=uart[8250],io|mmio|mmio16|mmio32,<addr>[,<options>]
453 * console=uart[8250],0x<addr>[,<options>]
465 char match[] = "uart"; /* 8250-specific earlycon name */ in univ8250_console_match()
695 struct uart_8250_port *uart; in serial8250_register_8250_port() local
703 uart = serial8250_find_match_or_unused(&up->port); in serial8250_register_8250_port()
704 if (!uart) { in serial8250_register_8250_port()
709 uart = serial8250_setup_port(nr_uarts); in serial8250_register_8250_port()
[all …]
H A D8250_lpc18xx.c3 * Serial port driver for NXP LPC18xx/43xx UART
93 struct uart_8250_port uart; in lpc18xx_serial_probe() local
103 memset(&uart, 0, sizeof(uart)); in lpc18xx_serial_probe()
105 uart.port.membase = devm_ioremap(&pdev->dev, res->start, in lpc18xx_serial_probe()
107 if (!uart.port.membase) in lpc18xx_serial_probe()
116 dev_err(&pdev->dev, "uart clock not found\n"); in lpc18xx_serial_probe()
134 dev_err(&pdev->dev, "unable to enable uart clock\n"); in lpc18xx_serial_probe()
141 spin_lock_init(&uart.port.lock); in lpc18xx_serial_probe()
142 uart.port.dev = &pdev->dev; in lpc18xx_serial_probe()
143 uart.port.mapbase = res->start; in lpc18xx_serial_probe()
[all …]
H A D8250_ingenic.c6 * Ingenic SoC UART support
142 * oscillator and some peripherals including UART, which will in jz4750_early_console_setup()
153 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
156 OF_EARLYCON_DECLARE(jz4750_uart, "ingenic,jz4750-uart",
159 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
162 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
165 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
168 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
177 /* UART module enable */ in ingenic_uart_serial_out()
233 struct uart_8250_port uart = {}; in ingenic_uart_probe() local
[all …]
H A D8250_keba.c5 * Driver for KEBA UART FPGA IP core
129 * Set DTR line configuration of 95x UART to DTR mode (1,0). in kuart_rs485_config()
138 * Set DTR line configuration of 95x UART to DTR mode (0,0). in kuart_rs485_config()
163 struct uart_8250_port uart = {}; in kuart_probe() local
176 * map only memory in front of UART registers, UART registers will be in kuart_probe()
196 spin_lock_init(&uart.port.lock); in kuart_probe()
197 uart.port.dev = dev; in kuart_probe()
198 uart.port.mapbase = kuart->auxdev->io.start + KUART_BASE; in kuart_probe()
199 uart.port.irq = kuart->auxdev->irq; in kuart_probe()
200 uart.port.uartclk = KUART_CLK; in kuart_probe()
[all …]
H A D8250_pxa.c56 { .compatible = "mrvl,pxa-uart", },
57 { .compatible = "mrvl,mmp-uart", },
62 /* Uart divisor latch write */
92 struct uart_8250_port uart = {}; in serial_pxa_probe() local
113 uart.port.type = PORT_XSCALE; in serial_pxa_probe()
114 uart.port.mapbase = mmres->start; in serial_pxa_probe()
115 uart.port.flags = UPF_IOREMAP | UPF_SKIP_TEST | UPF_FIXED_TYPE; in serial_pxa_probe()
116 uart.port.dev = &pdev->dev; in serial_pxa_probe()
117 uart.port.uartclk = clk_get_rate(data->clk); in serial_pxa_probe()
118 uart.port.pm = serial_pxa_pm; in serial_pxa_probe()
[all …]
H A D8250_dfl.c3 * Driver for FPGA UART
52 static int dfl_uart_get_params(struct dfl_device *dfl_dev, struct uart_8250_port *uart) in dfl_uart_get_params() argument
63 uart->port.uartclk = clk_freq; in dfl_uart_get_params()
71 uart->port.type = PORT_ALTR_16550_F32; in dfl_uart_get_params()
75 uart->port.type = PORT_ALTR_16550_F64; in dfl_uart_get_params()
79 uart->port.type = PORT_ALTR_16550_F128; in dfl_uart_get_params()
90 uart->port.regshift = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_SHIFT, reg_layout); in dfl_uart_get_params()
94 uart->port.iotype = UPIO_MEM32; in dfl_uart_get_params()
98 uart->port.iotype = UPIO_MEM16; in dfl_uart_get_params()
112 struct uart_8250_port uart = { }; in dfl_uart_probe() local
[all …]
H A D8250_hp300.c63 /* Offset to UART registers from base of DCA */
160 struct uart_8250_port uart; in hpdca_init_one() local
169 memset(&uart, 0, sizeof(uart)); in hpdca_init_one()
172 uart.port.iotype = UPIO_MEM; in hpdca_init_one()
173 uart.port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF; in hpdca_init_one()
174 uart.port.irq = d->ipl; in hpdca_init_one()
175 uart.port.uartclk = HPDCA_BAUD_BASE * 16; in hpdca_init_one()
176 uart.port.mapbase = (d->resource.start + UART_OFFSET); in hpdca_init_one()
177 uart.port.membase = (char *)(uart.port.mapbase + DIO_VIRADDRBASE); in hpdca_init_one()
178 uart.port.regshift = 1; in hpdca_init_one()
[all …]
/linux/arch/mips/kernel/
H A Dcps-vec-ns16550.S32 * _mips_cps_putc() - write a character to the UART
34 * @t9: UART base address
45 * _mips_cps_puts() - write a string to the UART
47 * @t9: UART base address
49 * Write a null-terminated ASCII string to the UART.
65 * _mips_cps_putx4 - write a 4b hex value to the UART
66 * @a0: the 4b value to write to the UART
67 * @t9: UART base address
69 * Write a single hexadecimal character to the UART.
82 * _mips_cps_putx8 - write an 8b hex value to the UART
[all …]
/linux/arch/arm/include/debug/
H A Dtegra.S45 #define checkuart(rp, rv, lhu, bit, uart) \ argument
50 /* Test UART's reset bit */ \
52 /* If set, can't use UART; jump to save no UART */ \
58 /* Test UART's clock enable bit */ \
60 /* If clear, can't use UART; jump to save no UART */ \
62 /* Passed all tests, load address of UART registers */ \
63 ldr rp, =TEGRA_UART##uart##_BASE ; \
64 /* Jump to save UART address */ \
85 cmp \rv, #2 @ 2 and 3 mean DCC, UART
89 11: lsr \rv, \rp, #15 @ 17:15 are UART ID
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dmediatek,uart-dma.yaml4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
7 title: MediaTek UART APDMA controller
13 The MediaTek UART APDMA controller provides DMA capabilities
14 for the UART peripheral bus.
24 - mediatek,mt2712-uart-dma
25 - mediatek,mt6795-uart-dma
26 - mediatek,mt8365-uart-dma
27 - mediatek,mt8516-uart-dma
28 - const: mediatek,mt6577-uart-dma
30 - mediatek,mt6577-uart-dma
[all …]

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