Home
last modified time | relevance | path

Searched full:uart (Results 1 – 25 of 1073) sorted by relevance

12345678910>>...43

/linux/Documentation/devicetree/bindings/serial/
H A Dmediatek,uart.yaml4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
26 - mediatek,mt2701-uart
27 - mediatek,mt2712-uart
28 - mediatek,mt6572-uart
29 - mediatek,mt6580-uart
30 - mediatek,mt6582-uart
31 - mediatek,mt6589-uart
[all …]
H A Dsamsung_uart.yaml7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
22 - apple,s5l-uart
23 - axis,artpec8-uart
24 - google,gs101-uart
25 - samsung,s3c6400-uart
26 - samsung,s5pv210-uart
27 - samsung,exynos4210-uart
28 - samsung,exynos5433-uart
29 - samsung,exynos850-uart
[all …]
H A Dfsl-imx-uart.yaml4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
15 - const: fsl,imx1-uart
16 - const: fsl,imx21-uart
19 - fsl,imx25-uart
20 - fsl,imx27-uart
21 - fsl,imx31-uart
22 - fsl,imx35-uart
23 - fsl,imx50-uart
24 - fsl,imx51-uart
[all …]
H A Dmarvell,armada-3700-uart.yaml4 $id: http://devicetree.org/schemas/serial/marvell,armada-3700-uart.yaml#
7 title: Marvell Armada-3700 UART
13 Marvell UART is a non standard UART used in some of Marvell EBU SoCs (e.g.
19 - marvell,armada-3700-uart
20 - marvell,armada-3700-uart-ext
28 UART reference clock used to derive the baud rate. If absent, only fixed
34 - description: UART sum interrupt
35 - description: UART TX interrupt
36 - description: UART RX interrupt
55 const: marvell,armada-3700-uart-ext
[all …]
H A Dbrcm,bcm7271-uart.yaml4 $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
16 The Broadcom UART is based on the basic 8250 UART but with
24 - brcm,bcm7271-uart
25 - brcm,bcm7278-uart
32 description: The UART register block and optionally the DMA register blocks.
35 - const: uart
37 - const: uart
54 description: The UART interrupt and optionally the DMA interrupt.
57 - const: uart
74 compatible = "brcm,bcm7271-uart";
[all …]
H A Dingenic,uart.yaml4 $id: http://devicetree.org/schemas/serial/ingenic,uart.yaml#
7 title: Ingenic SoCs UART controller
22 - ingenic,jz4740-uart
23 - ingenic,jz4750-uart
24 - ingenic,jz4760-uart
25 - ingenic,jz4780-uart
26 - ingenic,x1000-uart
29 - ingenic,jz4770-uart
30 - ingenic,jz4775-uart
31 - const: ingenic,jz4760-uart
[all …]
H A Dsifive-serial.yaml7 title: SiFive asynchronous serial interface (UART)
21 - sifive,fu540-c000-uart
22 - sifive,fu740-c000-uart
27 Should be something similar to "sifive,<chip>-uart"
28 for the UART as integrated on a particular chip,
29 and "sifive,uart<version>" for the general UART IP
32 UART HDL that corresponds to the IP block version
35 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
58 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
H A Drenesas,em-uart.yaml4 $id: http://devicetree.org/schemas/serial/renesas,em-uart.yaml#
7 title: Renesas EMMA Mobile UART Interface
17 - renesas,r9a09g011-uart # RZ/V2M
18 - const: renesas,em-uart # generic EMMA Mobile compatible UART
21 - const: renesas,em-uart # generic EMMA Mobile compatible UART
32 - description: UART functional clock
55 const: renesas,r9a09g011-uart
69 compatible = "renesas,em-uart";
/linux/Documentation/devicetree/bindings/dma/
H A Dmediatek,uart-dma.yaml4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
7 title: MediaTek UART APDMA controller
14 The MediaTek UART APDMA controller provides DMA capabilities
15 for the UART peripheral bus.
25 - mediatek,mt2712-uart-dma
26 - mediatek,mt6795-uart-dma
27 - mediatek,mt8173-uart-dma
28 - mediatek,mt8183-uart-dma
29 - mediatek,mt8365-uart-dma
30 - mediatek,mt8516-uart-dma
[all …]
/linux/drivers/tty/serial/
H A Dtimbuart.c3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
55 struct timbuart_port *uart = in timbuart_start_tx() local
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
115 struct timbuart_port *uart = in timbuart_handle_tx_port() local
134 *ier |= uart->last_ier & TXFLAGS; in timbuart_handle_tx_port()
171 struct timbuart_port *uart = from_tasklet(uart, t, tasklet); in timbuart_tasklet() local
174 uart_port_lock(&uart->port); in timbuart_tasklet()
176 isr = ioread32(uart->port.membase + TIMBUART_ISR); in timbuart_tasklet()
177 dev_dbg(uart->port.dev, "%s ISR: %x\n", __func__, isr); in timbuart_tasklet()
[all …]
H A Dliteuart.c73 struct liteuart_port *uart = to_liteuart_port(port); in liteuart_update_irq_reg() local
76 uart->irq_reg |= mask; in liteuart_update_irq_reg()
78 uart->irq_reg &= ~mask; in liteuart_update_irq_reg()
81 litex_write8(port->membase + OFF_EV_ENABLE, uart->irq_reg); in liteuart_update_irq_reg()
96 struct liteuart_port *uart = to_liteuart_port(port); in liteuart_stop_rx() local
99 timer_delete(&uart->timer); in liteuart_stop_rx()
133 struct liteuart_port *uart = data; in liteuart_interrupt() local
134 struct uart_port *port = &uart->port; in liteuart_interrupt()
143 isr = litex_read8(port->membase + OFF_EV_PENDING) & uart->irq_reg; in liteuart_interrupt()
155 struct liteuart_port *uart = timer_container_of(uart, t, timer); in liteuart_timer() local
[all …]
H A Dvt8500_serial.c28 * UART Register offsets
38 #define VT8500_URUSR 0x001c /* UART status */
96 struct uart_port uart; member
126 uart); in vt8500_stop_tx()
136 uart); in vt8500_stop_rx()
146 uart); in vt8500_enable_ms()
210 uart); in vt8500_start_tx()
282 container_of(port, struct vt8500_port, uart); in vt8500_set_baud_rate()
306 container_of(port, struct vt8500_port, uart); in vt8500_startup()
325 container_of(port, struct vt8500_port, uart); in vt8500_shutdown()
[all...]
/linux/drivers/tty/serial/8250/
H A D8250_tegra.c46 struct tegra_uart *uart; in tegra_uart_probe() local
51 uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL); in tegra_uart_probe()
52 if (!uart) in tegra_uart_probe()
84 uart->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); in tegra_uart_probe()
85 if (IS_ERR(uart->rst)) in tegra_uart_probe()
86 return PTR_ERR(uart->rst); in tegra_uart_probe()
89 uart->clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
90 if (IS_ERR(uart->clk)) { in tegra_uart_probe()
95 ret = clk_prepare_enable(uart->clk); in tegra_uart_probe()
99 port->uartclk = clk_get_rate(uart->clk); in tegra_uart_probe()
[all …]
H A D8250_lpc18xx.c3 * Serial port driver for NXP LPC18xx/43xx UART
93 struct uart_8250_port uart; in lpc18xx_serial_probe() local
103 memset(&uart, 0, sizeof(uart)); in lpc18xx_serial_probe()
105 uart.port.membase = devm_ioremap(&pdev->dev, res->start, in lpc18xx_serial_probe()
107 if (!uart.port.membase) in lpc18xx_serial_probe()
116 dev_err(&pdev->dev, "uart clock not found\n"); in lpc18xx_serial_probe()
134 dev_err(&pdev->dev, "unable to enable uart clock\n"); in lpc18xx_serial_probe()
141 spin_lock_init(&uart.port.lock); in lpc18xx_serial_probe()
142 uart.port.dev = &pdev->dev; in lpc18xx_serial_probe()
143 uart.port.mapbase = res->start; in lpc18xx_serial_probe()
[all …]
H A D8250_ingenic.c6 * Ingenic SoC UART support
142 * oscillator and some peripherals including UART, which will in jz4750_early_console_setup()
153 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
156 OF_EARLYCON_DECLARE(jz4750_uart, "ingenic,jz4750-uart",
159 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
162 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
165 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
168 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
177 /* UART module enable */ in ingenic_uart_serial_out()
233 struct uart_8250_port uart = {}; in ingenic_uart_probe() local
[all …]
H A D8250_keba.c5 * Driver for KEBA UART FPGA IP core
140 * Set DTR line configuration of 95x UART to DTR mode (1,0). in kuart_rs485_config()
149 * Set DTR line configuration of 95x UART to DTR mode (0,0). in kuart_rs485_config()
174 struct uart_8250_port uart = {}; in kuart_probe() local
187 * map only memory in front of UART registers, UART registers will be in kuart_probe()
207 spin_lock_init(&uart.port.lock); in kuart_probe()
208 uart.port.dev = dev; in kuart_probe()
209 uart.port.mapbase = kuart->auxdev->io.start + KUART_BASE; in kuart_probe()
210 uart.port.irq = kuart->auxdev->irq; in kuart_probe()
211 uart.port.uartclk = KUART_CLK; in kuart_probe()
[all …]
H A D8250_hp300.c63 /* Offset to UART registers from base of DCA */
160 struct uart_8250_port uart; in hpdca_init_one() local
169 memset(&uart, 0, sizeof(uart)); in hpdca_init_one()
172 uart.port.iotype = UPIO_MEM; in hpdca_init_one()
173 uart.port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF; in hpdca_init_one()
174 uart.port.irq = d->ipl; in hpdca_init_one()
175 uart.port.uartclk = HPDCA_BAUD_BASE * 16; in hpdca_init_one()
176 uart.port.mapbase = (d->resource.start + UART_OFFSET); in hpdca_init_one()
177 uart.port.membase = (char *)(uart.port.mapbase + DIO_VIRADDRBASE); in hpdca_init_one()
178 uart.port.regshift = 1; in hpdca_init_one()
[all …]
H A D8250_pxa.c56 { .compatible = "mrvl,pxa-uart", },
57 { .compatible = "mrvl,mmp-uart", },
62 /* Uart divisor latch write */
92 struct uart_8250_port uart = {}; in serial_pxa_probe() local
113 uart.port.type = PORT_XSCALE; in serial_pxa_probe()
114 uart.port.mapbase = mmres->start; in serial_pxa_probe()
115 uart.port.flags = UPF_IOREMAP | UPF_SKIP_TEST | UPF_FIXED_TYPE; in serial_pxa_probe()
116 uart.port.dev = &pdev->dev; in serial_pxa_probe()
117 uart.port.uartclk = clk_get_rate(data->clk); in serial_pxa_probe()
118 uart.port.pm = serial_pxa_pm; in serial_pxa_probe()
[all …]
H A D8250_dfl.c3 * Driver for FPGA UART
51 static int dfl_uart_get_params(struct dfl_device *dfl_dev, struct uart_8250_port *uart) in dfl_uart_get_params() argument
62 uart->port.uartclk = clk_freq; in dfl_uart_get_params()
70 uart->port.type = PORT_ALTR_16550_F32; in dfl_uart_get_params()
74 uart->port.type = PORT_ALTR_16550_F64; in dfl_uart_get_params()
78 uart->port.type = PORT_ALTR_16550_F128; in dfl_uart_get_params()
89 uart->port.regshift = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_SHIFT, reg_layout); in dfl_uart_get_params()
93 uart->port.iotype = UPIO_MEM32; in dfl_uart_get_params()
97 uart->port.iotype = UPIO_MEM16; in dfl_uart_get_params()
111 struct uart_8250_port uart = { }; in dfl_uart_probe() local
[all …]
H A D8250_ni.c3 * NI 16550 UART Driver
5 * The National Instruments (NI) 16550 is a UART that is compatible with the
257 static u8 ni16550_read_fifo_size(struct uart_8250_port *uart, int reg) in ni16550_read_fifo_size() argument
259 u8 value = serial_in(uart, reg); in ni16550_read_fifo_size()
277 struct uart_8250_port *uart __free(kfree) = NULL; in ni16550_probe()
287 uart = kzalloc_obj(*uart); in ni16550_probe()
288 if (!uart) in ni16550_probe()
295 spin_lock_init(&uart->port.lock); in ni16550_probe()
297 ret = ni16550_get_regs(pdev, &uart->port); in ni16550_probe()
302 serial8250_set_defaults(uart); in ni16550_probe()
[all …]
H A D8250_pericom.c2 /* Driver for Pericom UART */
89 struct uart_8250_port uart; in pericom8250_probe() local
113 memset(&uart, 0, sizeof(uart)); in pericom8250_probe()
115 uart.port.dev = &pdev->dev; in pericom8250_probe()
116 uart.port.irq = pdev->irq; in pericom8250_probe()
117 uart.port.private_data = pericom; in pericom8250_probe()
118 uart.port.iotype = UPIO_PORT; in pericom8250_probe()
119 uart.port.uartclk = 921600 * 16; in pericom8250_probe()
120 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; in pericom8250_probe()
121 uart.port.set_divisor = pericom_do_set_divisor; in pericom8250_probe()
[all …]
/linux/arch/mips/kernel/
H A Dcps-vec-ns16550.S32 * _mips_cps_putc() - write a character to the UART
34 * @t9: UART base address
45 * _mips_cps_puts() - write a string to the UART
47 * @t9: UART base address
49 * Write a null-terminated ASCII string to the UART.
65 * _mips_cps_putx4 - write a 4b hex value to the UART
66 * @a0: the 4b value to write to the UART
67 * @t9: UART base address
69 * Write a single hexadecimal character to the UART.
82 * _mips_cps_putx8 - write an 8b hex value to the UART
[all …]
/linux/arch/arm/include/debug/
H A Dtegra.S45 #define checkuart(rp, rv, lhu, bit, uart) \ argument
50 /* Test UART's reset bit */ \
52 /* If set, can't use UART; jump to save no UART */ \
58 /* Test UART's clock enable bit */ \
60 /* If clear, can't use UART; jump to save no UART */ \
62 /* Passed all tests, load address of UART registers */ \
63 ldr rp, =TEGRA_UART##uart##_BASE ; \
64 /* Jump to save UART address */ \
85 cmp \rv, #2 @ 2 and 3 mean DCC, UART
89 11: lsr \rv, \rp, #15 @ 17:15 are UART ID
[all …]
/linux/tools/arch/x86/dell-uart-backlight-emulator/
H A DREADME1 Emulator for DELL0501 UART attached backlight controller
5 board connected to an UART.
7 In DSDT this uart port will be defined as:
12 With the DELL0501 indicating that we are dealing with an UART with
16 the drivers/platform/x86/dell/dell-uart-backlight.c driver without access
20 1. A (desktop) PC with a 16550 UART on the motherboard and a standard DB9
21 connector connected to this UART.
25 4. A DSDT overlay for the desktop PC replacing the _HID of the 16550 UART
32 ./dell-uart-backlight-emulator <path-to-/dev/tty*S#-for-second-port>
36 ./dell-uart-backlight-emulator /dev/ttyUSB0
[all …]
/linux/Documentation/devicetree/bindings/soc/aspeed/
H A Duart-routing.yaml6 $id: http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#
9 title: Aspeed UART Routing Controller
16 The Aspeed UART routing control allow to dynamically route the inputs for
19 This allows, for example, to connect the output of UART to another UART.
31 - aspeed,ast2400-uart-routing
32 - aspeed,ast2500-uart-routing
33 - aspeed,ast2600-uart-routing
52 uart_routing: uart-routing@98 {
53 compatible = "aspeed,ast2600-uart-routing";

12345678910>>...43