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/linux/drivers/tty/serial/8250/
H A D8250_ingenic.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
6 * Ingenic SoC UART support
26 int fifosize; member
46 return readl(port->membase + (offset << 2)); in early_in()
51 writel(value, port->membase + (offset << 2)); in early_out()
68 uart_console_write(&early_device->port, s, count, in ingenic_early_console_write()
82 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL); in ingenic_early_console_setup_clock()
86 dev->port.uartclk = be32_to_cpup(prop); in ingenic_early_console_setup_clock()
92 struct uart_port *port = &dev->port; in ingenic_earlycon_setup_tail()
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H A D8250_of.c1 // SPDX-License-Identifier: GPL-2.0+
54 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2; in npcm_get_divisor()
59 port->get_divisor = npcm_get_divisor; in npcm_setup()
60 port->startup = npcm_startup; in npcm_setup()
73 struct uart_8250_port *port8250 = serial8250_get_port(info->line); in of_platform_serial_clk_notifier_cb()
77 serial8250_update_uartclk(&port8250->port, ndata->new_rate); in of_platform_serial_clk_notifier_cb()
92 struct device *dev = &ofdev->dev; in of_platform_serial_setup()
93 struct device_node *np = dev->of_node; in of_platform_serial_setup()
94 struct uart_port *port = &up->port; in of_platform_serial_setup()
100 pm_runtime_enable(&ofdev->dev); in of_platform_serial_setup()
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H A D8250_dw.c1 // SPDX-License-Identifier: GPL-2.0+
10 * raised, the LCR needs to be rewritten and the uart status register read.
35 #define OCTEON_UART_USR 0x27 /* UART Status Register */
92 struct dw8250_data *d = to_dw8250_data(p->private_data);
96 value |= d->msr_mask_on;
97 value &= ~d->msr_mask_off;
105 struct dw8250_data *d = to_dw8250_data(p->private_data); in clk_to_dw8250_data()
108 if (d->uart_16550_compatibl in clk_to_dw8250_data()
696 struct uart_8250_port uart = {}, *up = &uart; dw8250_probe() local
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H A D8250_port.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
43 * Here we define the default xmit fifo size used for each type of UART.
236 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
237 * workaround of errata A-008006 which states that tx_loadsz should
249 .name = "Palmchip BK-3103",
307 .name = "Broadcom BCM7271 UART",
3267 unsigned int fifosize = up->tx_loadsz; serial8250_console_fifo_write() local
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H A D8250_pxa.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS
37 serial8250_suspend_port(data->line); in serial_pxa_suspend()
46 serial8250_resume_port(data->line); in serial_pxa_resume()
56 { .compatible = "mrvl,pxa-uart", },
57 { .compatible = "mrvl,mmp-uart", },
62 /* Uart divisor latch write */
82 struct pxa8250_data *data = port->private_data; in serial_pxa_pm()
85 clk_prepare_enable(data->clk); in serial_pxa_pm()
87 clk_disable_unprepare(data->clk); in serial_pxa_pm()
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H A D8250_uniphier.c1 // SPDX-License-Identifier: GPL-2.0+
17 * - MMIO32 (regshift = 2)
18 * - FCR is not at 2, but 3
19 * - LCR and MCR are not at 3 and 4, they share 4
20 * - No SCR (Instead, CHAR can be used as a scratch register)
21 * - Divisor latch at 9, no divisor latch access bit
43 if (!device->port.membase) in uniphier_early_console_setup()
44 return -ENODEV; in uniphier_early_console_setup()
47 device->port.iotype = UPIO_MEM32; in uniphier_early_console_setup()
48 device->port.regshift = UNIPHIER_UART_REGSHIFT; in uniphier_early_console_setup()
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H A D8250_ni.c1 // SPDX-License-Identifier: GPL-2.0+
3 * NI 16550 UART Driver
5 * The National Instruments (NI) 16550 is a UART that is compatible with the
7 * for RS-485 transceiver control. This driver implements support for the
10 * Copyright 2012-2023 National Instruments Corporation
31 /* TFS - TX FIFO Size */
33 /* RFS - RX FIFO Size */
36 /* PMR - Port Mode Register */
38 /* PMR[1:0] - Port Capabilities */
41 #define NI16550_PMR_CAP_RS232 FIELD_PREP(NI16550_PMR_CAP_MASK, 1) /* RS-232 capable */
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/linux/Documentation/devicetree/bindings/serial/
H A Dsamsung_uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
21 - enum:
22 - apple,s5l-uart
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/linux/drivers/tty/serial/
H A Dsamsung_tty.c1 // SPDX-License-Identifier: GPL-2.0
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
12 * UERSTAT register in the UART blocks, and keeps marking some of the
21 * BJD, 04-Nov-2004
28 #include <linux/dma-mapping.h>
48 /* UART name and device definitions */
77 unsigned int fifosize; member
98 const unsigned int fifosize[UART_NR]; global() member
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H A Dsccnxp.c1 // SPDX-License-Identifier: GPL-2.0+
24 #include <linux/platform_data/serial-sccnxp.h>
27 #define SCCNXP_NAME "uart-sccnxp"
93 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
94 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
106 unsigned int fifosize; member
112 struct uart_driver uart; member
142 .fifosize = 3,
153 .fifosize = 3,
164 .fifosize = 3,
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H A Dbcm63xx_uart.c1 // SPDX-License-Identifier: GPL-2.0
7 * Serial driver for BCM63xx integrated UART.
37 * - rx fifo full
38 * - rx fifo above threshold
39 * - rx fifo not empty for too long
53 * - tx fifo empty
54 * - tx fifo below threshold
71 * handy uart registe
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H A Dmeson_uart.c1 // SPDX-License-Identifier: GPL-2.0
102 val = readl(port->membase + AML_UART_STATUS); in meson_uart_tx_empty()
111 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
113 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
120 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
122 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
130 free_irq(port->irq, port); in meson_uart_shutdown()
134 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
137 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
144 struct tty_port *tport = &port->state->port; in meson_uart_start_tx()
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H A Dtegra-utc.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 // NVIDIA Tegra UTC (UART Trace Controller) driver.
69 unsigned int fifosize; member
76 void __iomem *addr = tup->rx_base + offset; in tegra_utc_rx_readl()
83 void __iomem *addr = tup->rx_base + offset; in tegra_utc_rx_writel()
90 void __iomem *addr = tup->tx_base + offset; in tegra_utc_tx_readl()
97 void __iomem *addr = tup->tx_base + offset; in tegra_utc_tx_writel()
104 tup->tx_irqmask = TEGRA_UTC_INTR_REQ; in tegra_utc_enable_tx_irq()
106 tegra_utc_tx_writel(tup, tup->tx_irqmask, TEGRA_UTC_INTR_MASK); in tegra_utc_enable_tx_irq()
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H A Dpch_uart.c1 // SPDX-License-Identifier: GPL-2.0
37 /* Set the max number of UART port
243 * struct pch_uart_driver_data - private data structure for UART-DMA
244 * @port_type: The type of UART port
245 * @line_no: UART port line number (0, 1, 2...)
296 struct eg20t_port *priv = file->private_dat in port_show_regs()
1653 int fifosize; pch_uart_init_port() local
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H A D21285.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the serial port on the 21285 StrongArm-110 core logic chip.
19 #include <asm/mach-types.h>
42 static const char serial21285_name[] = "Footbridge UART";
46 * this, use bits of the private_data pointer of the uart port structure.
53 unsigned long *private_data = (unsigned long *)&port->private_data; in is_enabled()
62 unsigned long *private_data = (unsigned long *)&port->private_data; in enable()
69 unsigned long *private_data = (unsigned long *)&port->private_data; in disable()
84 * BAUD_BASE / baud - 1
88 * int(BAUD_BASE / baud - 0.5) ->
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H A Dmilbeaut_usio.c1 // SPDX-License-Identifier: GPL-2.0
15 #define USIO_NAME "mlb-usio-uart"
67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_stop_tx()
68 port->membase + MLB_USIO_REG_FCR); in mlb_usio_stop_tx()
69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE, in mlb_usio_stop_tx()
70 port->membase + MLB_USIO_REG_SCR); in mlb_usio_stop_tx()
75 struct tty_port *tport = &port->state->port; in mlb_usio_tx_chars()
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_tx_chars()
79 port->membase + MLB_USIO_REG_FCR); in mlb_usio_tx_chars()
80 writeb(readb(port->membase + MLB_USIO_REG_SCR) & in mlb_usio_tx_chars()
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H A Dliteuart.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
25 * The definitions below are true for LiteX SoC configured for 8-bit CSR Bus,
26 * 32-bit aligned.
73 struct liteuart_port *uart = to_liteuart_port(port); in liteuart_update_irq_reg() local
76 uart->irq_reg |= mask; in liteuart_update_irq_reg()
78 uart->irq_reg &= ~mask; in liteuart_update_irq_reg()
80 if (port->irq) in liteuart_update_irq_reg()
81 litex_write8(port->membase + OFF_EV_ENABLE, uart->irq_reg); in liteuart_update_irq_reg()
96 struct liteuart_port *uart = to_liteuart_port(port); in liteuart_stop_rx() local
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H A Dtimbuart.c1 // SPDX-License-Identifier: GPL-2.0
3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
55 struct timbuart_port *uart = in timbuart_start_tx() local
58 /* do not transfer anything here -> fire off the tasklet */ in timbuart_start_tx()
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
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H A Dar933x_uart.c1 // SPDX-License-Identifier: GPL-2.0
3 * Atheros AR933X SoC built-in UART driver
31 #include <asm/mach-ath79/ar933x_uart.h>
35 #define DRIVER_NAME "ar933x-uart"
60 return readl(up->port.membase + offset); in ar933x_uart_read()
66 writel(value, up->port.membase + offset); in ar933x_uart_write()
98 up->ier |= AR933X_UART_INT_TX_EMPTY; in ar933x_uart_start_tx_interrupt()
99 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); in ar933x_uart_start_tx_interrupt()
104 up->ier &= ~AR933X_UART_INT_TX_EMPTY; in ar933x_uart_stop_tx_interrupt()
105 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); in ar933x_uart_stop_tx_interrupt()
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H A Dtegra-tcu.c1 // SPDX-License-Identifier: GPL-2.0
58 mbox_send_message(tcu->tx, msg); in tegra_tcu_write_one()
59 mbox_flush(tcu->tx, 1000); in tegra_tcu_write_one()
93 struct tegra_tcu *tcu = port->private_data; in tegra_tcu_uart_start_tx()
94 struct tty_port *tport = &port->state->port; in tegra_tcu_uart_start_tx()
99 count = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, in tegra_tcu_uart_start_tx()
165 struct tty_port *port = &tcu->port.state->port; in tegra_tcu_receive()
184 tcu = devm_kzalloc(&pdev->dev, sizeof(*tcu), GFP_KERNEL); in tegra_tcu_probe()
186 return -ENOMEM; in tegra_tcu_probe()
188 tcu->tx_client.dev = &pdev->dev; in tegra_tcu_probe()
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H A Domap-serial.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for OMAP-UART controller.
16 * this driver as required for the omap-platform.
38 #include <linux/platform_data/serial-omap.h>
79 #define OMAP_UART_DMA_CH_FREE -1
176 offset <<= up->port.regshift; in serial_in()
177 return readw(up->por in serial_in()
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H A Dpxa.c1 // SPDX-License-Identifier: GPL-2.0+
55 return readl(up->port.membase + offset); in serial_in()
61 writel(value, up->port.membase + offset); in serial_out()
68 up->ier |= UART_IER_MSI; in serial_pxa_enable_ms()
69 serial_out(up, UART_IER, up->ier); in serial_pxa_enable_ms()
76 if (up->ier & UART_IER_THRI) { in serial_pxa_stop_tx()
77 up->ier &= ~UART_IER_THRI; in serial_pxa_stop_tx()
78 serial_out(up, UART_IER, up->ie in serial_pxa_stop_tx()
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H A Dvt8500_serial.c1 // SPDX-License-Identifier: GPL-2.0
28 * UART Register offsets
38 #define VT8500_URUSR 0x001c /* UART status */
74 #define VT8500_CS8 (1 << 2) /* 8-bit data length (vs. 7-bit) */
83 #define VT8500_SWRTSCTS (1 << 11) /* Software-controlled RTS/CTS */
86 * Capability flags (driver-internal)
96 struct uart_port uart; member
106 * have been allocated as we can't use pdev->id in
114 writel(val, port->membase + off); in vt8500_write()
119 return readl(port->membase + off); in vt8500_read()
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/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov9.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov9.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,boot-mode.h>
12 #include <dt-binding
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H A Dexynos7885.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7885.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <1>;
17 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
34 interrupt-affinity = <&cpu0>,
42 arm-a73-pmu {
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