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Searched +full:uart +full:- +full:fifosize (Results 1 – 25 of 44) sorted by relevance

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/linux/drivers/tty/serial/8250/
H A D8250_ingenic.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
6 * Ingenic SoC UART support
26 int fifosize; member
46 return readl(port->membase + (offset << 2)); in early_in()
51 writel(value, port->membase + (offset << 2)); in early_out()
68 uart_console_write(&early_device->port, s, count, in ingenic_early_console_write()
82 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL); in ingenic_early_console_setup_clock()
86 dev->port.uartclk = be32_to_cpup(prop); in ingenic_early_console_setup_clock()
92 struct uart_port *port = &dev->port; in ingenic_earlycon_setup_tail()
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H A D8250_dw.c1 // SPDX-License-Identifier: GPL-2.0+
10 * raised, the LCR needs to be rewritten and the uart status register read.
34 #define OCTEON_UART_USR 0x27 /* UART Status Register */
91 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_modify_msr()
95 value |= d->msr_mask_on; in dw8250_modify_msr()
96 value &= ~d->msr_mask_off; in dw8250_modify_msr()
104 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_idle_exit()
107 if (d->uart_16550_compatible) in dw8250_idle_exit()
110 if (up->capabilities & UART_CAP_FIFO) in dw8250_idle_exit()
111 serial_port_out(p, UART_FCR, up->fcr); in dw8250_idle_exit()
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H A D8250_pxa.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS
37 serial8250_suspend_port(data->line); in serial_pxa_suspend()
46 serial8250_resume_port(data->line); in serial_pxa_resume()
56 { .compatible = "mrvl,pxa-uart", },
57 { .compatible = "mrvl,mmp-uart", },
62 /* Uart divisor latch write */
82 struct pxa8250_data *data = port->private_data; in serial_pxa_pm()
85 clk_prepare_enable(data->clk); in serial_pxa_pm()
87 clk_disable_unprepare(data->clk); in serial_pxa_pm()
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H A D8250_uniphier.c1 // SPDX-License-Identifier: GPL-2.0+
17 * - MMIO32 (regshift = 2)
18 * - FCR is not at 2, but 3
19 * - LCR and MCR are not at 3 and 4, they share 4
20 * - No SCR (Instead, CHAR can be used as a scratch register)
21 * - Divisor latch at 9, no divisor latch access bit
43 if (!device->port.membase) in uniphier_early_console_setup()
44 return -ENODEV; in uniphier_early_console_setup()
47 device->port.iotype = UPIO_MEM32; in uniphier_early_console_setup()
48 device->port.regshift = UNIPHIER_UART_REGSHIFT; in uniphier_early_console_setup()
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H A D8250_ni.c1 // SPDX-License-Identifier: GPL-2.0+
3 * NI 16550 UART Driver
5 * The National Instruments (NI) 16550 is a UART that is compatible with the
7 * for RS-485 transceiver control. This driver implements support for the
10 * Copyright 2012-2023 National Instruments Corporation
30 /* TFS - TX FIFO Size */
32 /* RFS - RX FIFO Size */
35 /* PMR - Port Mode Register */
37 /* PMR[1:0] - Port Capabilities */
40 #define NI16550_PMR_CAP_RS232 FIELD_PREP(NI16550_PMR_CAP_MASK, 1) /* RS-232 capable */
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/linux/Documentation/devicetree/bindings/serial/
H A Dsamsung_uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
21 - enum:
22 - apple,s5l-uart
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/linux/drivers/tty/serial/
H A Dsccnxp.c1 // SPDX-License-Identifier: GPL-2.0+
23 #include <linux/platform_data/serial-sccnxp.h>
26 #define SCCNXP_NAME "uart-sccnxp"
92 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
93 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
105 unsigned int fifosize; member
111 struct uart_driver uart; member
141 .fifosize = 3,
152 .fifosize = 3,
163 .fifosize = 3,
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H A Dmeson_uart.c1 // SPDX-License-Identifier: GPL-2.0
102 val = readl(port->membase + AML_UART_STATUS); in meson_uart_tx_empty()
111 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
113 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
120 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
122 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
130 free_irq(port->irq, port); in meson_uart_shutdown()
134 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
137 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
144 struct tty_port *tport = &port->state->port; in meson_uart_start_tx()
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H A Dmsm_serial.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/dma-mapping.h>
178 struct uart_port uart; member
192 return container_of(up, struct msm_port, uart); in to_msm_port()
198 writel_relaxed(val, port->membase + off); in msm_write()
204 return readl_relaxed(port->membase + off); in msm_read()
216 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxo()
228 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxoby4()
239 if (msm_port->is_uartdm) in msm_serial_set_mnd_regs()
242 if (port->uartclk == 19200000) in msm_serial_set_mnd_regs()
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H A Dtegra-utc.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 // NVIDIA Tegra UTC (UART Trace Controller) driver.
68 unsigned int fifosize; member
75 void __iomem *addr = tup->rx_base + offset; in tegra_utc_rx_readl()
82 void __iomem *addr = tup->rx_base + offset; in tegra_utc_rx_writel()
89 void __iomem *addr = tup->tx_base + offset; in tegra_utc_tx_readl()
96 void __iomem *addr = tup->tx_base + offset; in tegra_utc_tx_writel()
103 tup->tx_irqmask = TEGRA_UTC_INTR_REQ; in tegra_utc_enable_tx_irq()
105 tegra_utc_tx_writel(tup, tup->tx_irqmask, TEGRA_UTC_INTR_MASK); in tegra_utc_enable_tx_irq()
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H A D21285.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the serial port on the 21285 StrongArm-110 core logic chip.
19 #include <asm/mach-types.h>
42 static const char serial21285_name[] = "Footbridge UART";
46 * this, use bits of the private_data pointer of the uart port structure.
53 unsigned long *private_data = (unsigned long *)&port->private_data; in is_enabled()
62 unsigned long *private_data = (unsigned long *)&port->private_data; in enable()
69 unsigned long *private_data = (unsigned long *)&port->private_data; in disable()
84 * BAUD_BASE / baud - 1
88 * int(BAUD_BASE / baud - 0.5) ->
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H A Dmilbeaut_usio.c1 // SPDX-License-Identifier: GPL-2.0
15 #define USIO_NAME "mlb-usio-uart"
67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_stop_tx()
68 port->membase + MLB_USIO_REG_FCR); in mlb_usio_stop_tx()
69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE, in mlb_usio_stop_tx()
70 port->membase + MLB_USIO_REG_SCR); in mlb_usio_stop_tx()
75 struct tty_port *tport = &port->state->port; in mlb_usio_tx_chars()
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_tx_chars()
79 port->membase + MLB_USIO_REG_FCR); in mlb_usio_tx_chars()
80 writeb(readb(port->membase + MLB_USIO_REG_SCR) & in mlb_usio_tx_chars()
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H A Dliteuart.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
25 * The definitions below are true for LiteX SoC configured for 8-bit CSR Bus,
26 * 32-bit aligned.
73 struct liteuart_port *uart = to_liteuart_port(port); in liteuart_update_irq_reg() local
76 uart->irq_reg |= mask; in liteuart_update_irq_reg()
78 uart->irq_reg &= ~mask; in liteuart_update_irq_reg()
80 if (port->irq) in liteuart_update_irq_reg()
81 litex_write8(port->membase + OFF_EV_ENABLE, uart->irq_reg); in liteuart_update_irq_reg()
96 struct liteuart_port *uart = to_liteuart_port(port); in liteuart_stop_rx() local
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H A Dtimbuart.c1 // SPDX-License-Identifier: GPL-2.0
3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
55 struct timbuart_port *uart = in timbuart_start_tx() local
58 /* do not transfer anything here -> fire off the tasklet */ in timbuart_start_tx()
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
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H A Dar933x_uart.c1 // SPDX-License-Identifier: GPL-2.0
3 * Atheros AR933X SoC built-in UART driver
31 #include <asm/mach-ath79/ar933x_uart.h>
35 #define DRIVER_NAME "ar933x-uart"
60 return readl(up->port.membase + offset); in ar933x_uart_read()
66 writel(value, up->port.membase + offset); in ar933x_uart_write()
98 up->ier |= AR933X_UART_INT_TX_EMPTY; in ar933x_uart_start_tx_interrupt()
99 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); in ar933x_uart_start_tx_interrupt()
104 up->ier &= ~AR933X_UART_INT_TX_EMPTY; in ar933x_uart_stop_tx_interrupt()
105 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); in ar933x_uart_stop_tx_interrupt()
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H A Dtegra-tcu.c1 // SPDX-License-Identifier: GPL-2.0
58 mbox_send_message(tcu->tx, msg); in tegra_tcu_write_one()
59 mbox_flush(tcu->tx, 1000); in tegra_tcu_write_one()
93 struct tegra_tcu *tcu = port->private_data; in tegra_tcu_uart_start_tx()
94 struct tty_port *tport = &port->state->port; in tegra_tcu_uart_start_tx()
99 count = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, in tegra_tcu_uart_start_tx()
165 struct tty_port *port = &tcu->port.state->port; in tegra_tcu_receive()
184 tcu = devm_kzalloc(&pdev->dev, sizeof(*tcu), GFP_KERNEL); in tegra_tcu_probe()
186 return -ENOMEM; in tegra_tcu_probe()
188 tcu->tx_client.dev = &pdev->dev; in tegra_tcu_probe()
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H A Dvt8500_serial.c1 // SPDX-License-Identifier: GPL-2.0
28 * UART Register offsets
38 #define VT8500_URUSR 0x001c /* UART status */
74 #define VT8500_CS8 (1 << 2) /* 8-bit data length (vs. 7-bit) */
83 #define VT8500_SWRTSCTS (1 << 11) /* Software-controlled RTS/CTS */
86 * Capability flags (driver-internal)
96 struct uart_port uart; member
106 * have been allocated as we can't use pdev->id in
114 writel(val, port->membase + off); in vt8500_write()
119 return readl(port->membase + off); in vt8500_read()
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H A Dserial_port.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
27 !kfifo_is_empty(&port->state->port.xmit_fifo); in __serial_port_busy()
36 port = port_dev->port; in serial_port_runtime_resume()
38 if (port->flags & UPF_DEAD) in serial_port_runtime_resume()
43 if (!port_dev->tx_enabled) in serial_port_runtime_resume()
46 port->ops->start_tx(port); in serial_port_runtime_resume()
60 struct uart_port *port = port_dev->port; in serial_port_runtime_suspend()
64 if (port->flags & UPF_DEAD) in serial_port_runtime_suspend()
75 if (!port_dev->tx_enabled) { in serial_port_runtime_suspend()
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H A Dst-asc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * st-asc.c: ST Asynchronous serial controller (ASC) driver
5 * Copyright (C) 2003-2013 STMicroelectronics (R&D) Limited
26 #define DRIVER_NAME "st-asc"
48 /*---- UART Register definitions ------------------------------*/
144 /*---- Inline function definitions ---------------------------*/
154 return readl_relaxed(port->membase + offset); in asc_in()
156 return readl(port->membase + offset); in asc_in()
163 writel_relaxed(value, port->membase + offset); in asc_out()
165 writel(value, port->membase + offset); in asc_out()
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H A Dsunsab.c1 // SPDX-License-Identifier: GPL-2.0
11 * rates to be programmed into the UART. Also eliminated a lot of
13 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
15 * Ported to new 2.5.x UART layer.
50 struct uart_port port; /* Generic UART port */
75 * This assumes you have a 29.4912 MHz clock for your UART.
94 int timeout = up->tec_timeout; in sunsab_tec_wait()
96 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout) in sunsab_tec_wait()
102 int timeout = up->cec_timeout; in sunsab_cec_wait()
104 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout) in sunsab_cec_wait()
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H A Dowl-uart.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Copyright (c) 2016-2017 Andreas Färber
86 writel(val, port->membase + off); in owl_uart_write()
91 return readl(port->membase + off); in owl_uart_read()
205 port->icount.overrun++; in owl_uart_receive_chars()
209 port->icount.brk++; in owl_uart_receive_chars()
210 port->icount.frame++; in owl_uart_receive_chars()
212 stat &= port->read_status_mask; in owl_uart_receive_chars()
216 port->icount.rx++; in owl_uart_receive_chars()
223 if (!sysrq && (stat & port->ignore_status_mask) == 0) in owl_uart_receive_chars()
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H A Dmps2-uart.c1 // SPDX-License-Identifier: GPL-2.0
3 * MPS2 UART driver
27 #define DRIVER_NAME "mps2-uart"
87 writeb(val, mps_port->port.membase + off); in mps2_uart_write8()
94 return readb(mps_port->port.membase + off); in mps2_uart_read8()
101 writel_relaxed(val, mps_port->port.membase + off); in mps2_uart_write32()
147 * We've just unmasked the TX IRQ and now slow-starting via in mps2_uart_start_tx()
150 * point we switch to fully interrupt-driven TX. in mps2_uart_start_tx()
171 struct tty_port *tport = &port->state->port; in mps2_uart_rx_chars()
176 port->icount.rx++; in mps2_uart_rx_chars()
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H A Dserial-tegra.c1 // SPDX-License-Identifier: GPL-2.0
5 * High-speed serial driver for NVIDIA Tegra SoCs
7 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
16 #include <linux/dma-mapping.h>
56 * Tx fifo trigger level setting in tegra uart is in
57 * reverse way then conventional uart.
66 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
84 * @uart_max_port: Maximum number of UART ports
159 return readl(tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_read()
165 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_write()
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H A Dmux.c1 // SPDX-License-Identifier: GPL-2.0+
4 ** serial driver for the Mux console found in some PA-RISC servers.
7 ** (c) Copyright 2002 Hewlett-Packard Company
26 #include <asm/parisc-device.h>
63 #define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + IO_DATA_REG_OFFSET)
64 #define UART_GET_FIFO_CNT(p) __raw_readl((p)->membase + IO_DCOUNT_REG_OFFSET)
67 * get_mux_port_count - Get the number of available ports on the Mux.
82 /* If this is the built-in Mux for the K-Class (Eole CAP/MUX), in get_mux_port_count()
86 if(dev->id.hversion == 0x15) in get_mux_port_count()
89 status = pdc_iodc_read(&bytecnt, dev->hpa.start, 0, iodc_data, 32); in get_mux_port_count()
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H A Dsifive.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SiFive UART driver
5 * Copyright (C) 2018-2019 SiFive
8 * - drivers/tty/serial/pxa.c
9 * - drivers/tty/serial/amba-pl011.c
10 * - drivers/tty/serial/uartlite.c
11 * - drivers/tty/serial/omap-serial.c
12 * - drivers/pwm/pwm-sifive.c
15 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
16 * SiFive FE310-G000 v2p3
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