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/linux/drivers/scsi/qla4xxx/
H A Dql4_dbg.c83 (uint8_t) offsetof(struct isp_reg, u2.isp4010.ext_hw_conf), in qla4xxx_dump_registers()
84 readw(&ha->reg->u2.isp4010.ext_hw_conf)); in qla4xxx_dump_registers()
86 (uint8_t) offsetof(struct isp_reg, u2.isp4010.port_ctrl), in qla4xxx_dump_registers()
87 readw(&ha->reg->u2.isp4010.port_ctrl)); in qla4xxx_dump_registers()
89 (uint8_t) offsetof(struct isp_reg, u2.isp4010.port_status), in qla4xxx_dump_registers()
90 readw(&ha->reg->u2.isp4010.port_status)); in qla4xxx_dump_registers()
92 (uint8_t) offsetof(struct isp_reg, u2.isp4010.req_q_out), in qla4xxx_dump_registers()
93 readw(&ha->reg->u2.isp4010.req_q_out)); in qla4xxx_dump_registers()
95 (uint8_t) offsetof(struct isp_reg, u2.isp4010.gp_out), in qla4xxx_dump_registers()
96 readw(&ha->reg->u2.isp4010.gp_out)); in qla4xxx_dump_registers()
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H A Dql4_def.h943 &ha->reg->u2.isp4010.ext_hw_conf : in isp_ext_hw_conf()
944 &ha->reg->u2.isp4022.p0.ext_hw_conf); in isp_ext_hw_conf()
950 &ha->reg->u2.isp4010.port_status : in isp_port_status()
951 &ha->reg->u2.isp4022.p0.port_status); in isp_port_status()
957 &ha->reg->u2.isp4010.port_ctrl : in isp_port_ctrl()
958 &ha->reg->u2.isp4022.p0.port_ctrl); in isp_port_ctrl()
964 &ha->reg->u2.isp4010.port_err_status : in isp_port_error_status()
965 &ha->reg->u2.isp4022.p0.port_err_status); in isp_port_error_status()
971 &ha->reg->u2.isp4010.gp_out : in isp_gp_out()
972 &ha->reg->u2.isp4022.p0.gp_out); in isp_gp_out()
/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml24 u2 port0 0x0800 U2PHY_COM
29 u2 port1 0x1000 U2PHY_COM
34 u2 port2 0x1800 U2PHY_COM
39 u2 port0 0x0000 MISC
48 u2 port1 0x1000 MISC
57 u2 port2 0x2000 MISC
60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
183 - description: internal R efuse for U2 PHY or U3/PCIe PHY
188 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these
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H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
23 u2 port1 0x1000 MISC
26 u2 port2 0x2000 MISC
58 if only U2 ports provided, shouldn't use the property.
114 The value of slew rate calibrate (U2 phy)
121 The selection of VRT reference voltage (U2 phy)
128 The selection of HS_TX TERM reference voltage (U2 phy)
135 The selection of Internal Resistor (U2/U3 phy)
/linux/include/linux/
H A Duuid.h46 static inline bool guid_equal(const guid_t *u1, const guid_t *u2) in guid_equal() argument
48 return memcmp(u1, u2, sizeof(guid_t)) == 0; in guid_equal()
71 static inline bool uuid_equal(const uuid_t *u1, const uuid_t *u2) in uuid_equal() argument
73 return memcmp(u1, u2, sizeof(uuid_t)) == 0; in uuid_equal()
/linux/drivers/media/rc/keymaps/
H A Drc-kaiomy.c11 /* Kaiomy TVnPC U2
84 MODULE_DESCRIPTION("Kaiomy TVnPC U2 remote controller keytable");
/linux/arch/powerpc/include/asm/
H A Duninorth.h5 * This also includes U2 used on more recent MacRISC2/3
109 #define UNI_N_VERSION_INTREPID 0x00D2 /* Integrated U2 + K */
117 #define UNI_N_CLOCK_CNTL_ATA100 0x00000010 /* ATA-100 clock control (U2) */
/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3-common.yaml104 description: Set if we enable P3 OK for U2/SS Inactive quirk
164 snps,dis-u2-entry-quirk:
165 description: Set if link entering into U2 needs to be disabled
173 snps,dis-u2-freeclk-exists-quirk:
H A Drockchip,rk3399-dwc3.yaml107 snps,dis-u2-freeclk-exists-quirk;
/linux/drivers/usb/cdns3/
H A Dcdns3-gadget.h177 /* U2 state entry enable (used in SS mode). */
179 /* U2 state entry disable (used in SS mode). */
185 /* U2 state entry request (used in SS mode). */
338 * U2 state enable status (used in SS mode).
339 * 0 - Entering to U2 state disabled.
340 * 1 - Entering to U2 state enabled.
364 * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
441 /* SS link U2 state enter interrupt enable.*/
443 /* SS link U2 state exit interrupt enable.*/
494 /* U2 link state enter detected.*/
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/linux/drivers/parisc/
H A DKconfig24 bool "U2/Uturn I/O MMU"
29 U2/Uturn chip in "Virtual Mode" and use the I/O MMU.
/linux/arch/arm/boot/dts/st/
H A Dstm32mp15xx-dhcor-io1v8.dtsi9 /* Enpirion EP3A8LQI U2 on the DHCOR */
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-iot2050-usb3.dtsi26 snps,dis-u2-entry-quirk;
H A Dk3-am6548-iot2050-advanced-m2-bkey-usb3.dtso46 snps,dis-u2-entry-quirk;
H A Dk3-am654-pcie-usb3.dtso57 snps,dis-u2-entry-quirk;
/linux/drivers/crypto/intel/qat/qat_common/
H A Dicp_qat_fw_la.h303 } u2; member
314 } u2; member
/linux/arch/parisc/include/asm/
H A Ddma-mapping.h11 ** b) U2/Uturn cachable host memory NOP
/linux/arch/arm/kernel/
H A Datags_compat.c77 } u2; member
213 build_tag_list(params, &params->u2); in convert_to_tag_list()
/linux/drivers/usb/host/
H A Dxhci-port.h92 * - U2 to U0 L1 resume of USB 2.1 device complete
130 /* Inactivity timer value for transitions into U2 */
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-usb-lvstest24 Set "U2 timeout" for the downstream port where Link Layer
/linux/drivers/scsi/ibmvscsi_tgt/
H A Dibmvscsi_tgt.h353 #define h_vioctl(u, o, a, u1, u2, u3, u4) \ argument
354 plpar_hcall_norets(H_VIOCTL, u, o, a, u1, u2)
/linux/drivers/usb/core/
H A Dusb-acpi.c48 * Some USB3 ports may not support USB3 link power management U1/U2 states
50 * if U1 and U2 states should be disabled. Evaluate _DSM with:
H A Dport.c269 p = "u2"; in usb3_lpm_permit_show()
293 } else if (!strncmp(buf, "u2", 2)) { in usb3_lpm_permit_store()
304 * to make new u1 u2 setting take effect immediately. in usb3_lpm_permit_store()
/linux/lib/
H A Dstackdepot.c581 int stackdepot_memcmp(const unsigned long *u1, const unsigned long *u2, in stackdepot_memcmp() argument
584 for ( ; n-- ; u1++, u2++) { in stackdepot_memcmp()
585 if (*u1 != *u2) in stackdepot_memcmp()
/linux/arch/powerpc/include/asm/nohash/32/
H A Dpte-44x.h33 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR

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