xref: /linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml (revision 16e6a1a3cb3fa5fa11cd76a9d71235d927923329) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20          - enum:
21              - qcom,eliza-qmp-usb3-dp-phy
22          - const: qcom,sm8650-qmp-usb3-dp-phy
23      - items:
24          - enum:
25              - qcom,kaanapali-qmp-usb3-dp-phy
26          - const: qcom,sm8750-qmp-usb3-dp-phy
27      - enum:
28          - qcom,glymur-qmp-usb3-dp-phy
29          - qcom,hawi-qmp-usb3-dp-phy
30          - qcom,sar2130p-qmp-usb3-dp-phy
31          - qcom,sc7180-qmp-usb3-dp-phy
32          - qcom,sc7280-qmp-usb3-dp-phy
33          - qcom,sc8180x-qmp-usb3-dp-phy
34          - qcom,sc8280xp-qmp-usb43dp-phy
35          - qcom,sdm845-qmp-usb3-dp-phy
36          - qcom,sm6350-qmp-usb3-dp-phy
37          - qcom,sm8150-qmp-usb3-dp-phy
38          - qcom,sm8250-qmp-usb3-dp-phy
39          - qcom,sm8350-qmp-usb3-dp-phy
40          - qcom,sm8450-qmp-usb3-dp-phy
41          - qcom,sm8475-qmp-usb3-dp-phy
42          - qcom,sm8550-qmp-usb3-dp-phy
43          - qcom,sm8650-qmp-usb3-dp-phy
44          - qcom,sm8750-qmp-usb3-dp-phy
45          - qcom,x1e80100-qmp-usb3-dp-phy
46
47  reg:
48    maxItems: 1
49
50  clocks:
51    minItems: 4
52    maxItems: 5
53
54  clock-names:
55    minItems: 4
56    items:
57      - const: aux
58      - const: ref
59      - const: com_aux
60      - const: usb3_pipe
61      - const: cfg_ahb
62
63  power-domains:
64    maxItems: 1
65
66  resets:
67    maxItems: 2
68
69  reset-names:
70    items:
71      - const: phy
72      - const: common
73
74  vdda-phy-supply: true
75
76  vdda-pll-supply: true
77
78  refgen-supply: true
79
80  "#clock-cells":
81    const: 1
82    description:
83      See include/dt-bindings/phy/phy-qcom-qmp.h
84
85  "#phy-cells":
86    const: 1
87    description:
88      See include/dt-bindings/phy/phy-qcom-qmp.h
89
90  mode-switch: true
91  orientation-switch: true
92
93  ports:
94    $ref: /schemas/graph.yaml#/properties/ports
95
96    properties:
97      port@0:
98        $ref: /schemas/graph.yaml#/$defs/port-base
99        description: Output endpoint of the PHY
100        unevaluatedProperties: false
101
102        properties:
103          endpoint:
104            $ref: /schemas/graph.yaml#/$defs/endpoint-base
105            unevaluatedProperties: false
106
107          endpoint@0:
108            $ref: /schemas/graph.yaml#/$defs/endpoint-base
109            description: Display Port Output lanes of the PHY when used with static mapping,
110                         The entry index is the DP lanes index, and the number is the PHY
111                         signal in the order RX0, TX0, TX1, RX1.
112            unevaluatedProperties: false
113
114            properties:
115              # Static lane mappings are mutually exclusive with typec-mux/orientation-mux
116              data-lanes:
117                $ref: /schemas/types.yaml#/definitions/uint32-array
118                minItems: 2
119                maxItems: 4
120                oneOf:
121                  - items: # DisplayPort 1 lane, normal orientation
122                      - const: 3
123                  - items: # DisplayPort 1 lane, flipped orientation
124                      - const: 0
125                  - items: # DisplayPort 2 lanes, normal orientation
126                      - const: 3
127                      - const: 2
128                  - items: # DisplayPort 2 lanes, flipped orientation
129                      - const: 0
130                      - const: 1
131                  - items: # DisplayPort 4 lanes, normal orientation
132                      - const: 3
133                      - const: 2
134                      - const: 1
135                      - const: 0
136                  - items: # DisplayPort 4 lanes, flipped orientation
137                      - const: 0
138                      - const: 1
139                      - const: 2
140                      - const: 3
141            required:
142              - data-lanes
143
144          endpoint@1:
145            $ref: /schemas/graph.yaml#/$defs/endpoint-base
146            description: USB Output lanes of the PHY when used with static mapping.
147                         The entry index is the USB3 lane in the order TX then RX, and the
148                         number is the PHY signal in the order RX0, TX0, TX1, RX1.
149            unevaluatedProperties: false
150
151            properties:
152              # Static lane mappings are mutually exclusive with typec-mux/orientation-mux
153              data-lanes:
154                $ref: /schemas/types.yaml#/definitions/uint32-array
155                minItems: 2
156                oneOf:
157                  - items: # USB3, normal orientation
158                      - const: 1
159                      - const: 0
160                  - items: # USB3, flipped orientation
161                      - const: 2
162                      - const: 3
163
164            required:
165              - data-lanes
166
167      port@1:
168        $ref: /schemas/graph.yaml#/properties/port
169        description: Incoming endpoint from the USB controller
170
171      port@2:
172        $ref: /schemas/graph.yaml#/properties/port
173        description: Incoming endpoint from the DisplayPort controller
174
175required:
176  - compatible
177  - reg
178  - clocks
179  - clock-names
180  - resets
181  - reset-names
182  - vdda-phy-supply
183  - vdda-pll-supply
184  - "#clock-cells"
185  - "#phy-cells"
186
187allOf:
188  - $ref: /schemas/usb/usb-switch.yaml#
189  - if:
190      properties:
191        compatible:
192          enum:
193            - qcom,sc7180-qmp-usb3-dp-phy
194            - qcom,sdm845-qmp-usb3-dp-phy
195    then:
196      properties:
197        clocks:
198          maxItems: 5
199        clock-names:
200          maxItems: 5
201    else:
202      properties:
203        clocks:
204          maxItems: 4
205        clock-names:
206          maxItems: 4
207
208  - if:
209      properties:
210        compatible:
211          contains:
212            enum:
213              - qcom,glymur-qmp-usb3-dp-phy
214              - qcom,hawi-qmp-usb3-dp-phy
215              - qcom,sar2130p-qmp-usb3-dp-phy
216              - qcom,sc8280xp-qmp-usb43dp-phy
217              - qcom,sm6350-qmp-usb3-dp-phy
218              - qcom,sm8550-qmp-usb3-dp-phy
219              - qcom,sm8650-qmp-usb3-dp-phy
220              - qcom,sm8750-qmp-usb3-dp-phy
221              - qcom,x1e80100-qmp-usb3-dp-phy
222    then:
223      required:
224        - power-domains
225    else:
226      properties:
227        power-domains: false
228
229  - if:
230      properties:
231        compatible:
232          enum:
233            - qcom,glymur-qmp-usb3-dp-phy
234    then:
235      required:
236        - refgen-supply
237    else:
238      properties:
239        refgen-supply: false
240
241additionalProperties: false
242
243examples:
244  - |
245    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
246
247    phy@88eb000 {
248      compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
249      reg = <0x088eb000 0x4000>;
250
251      clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
252               <&gcc GCC_USB4_EUD_CLKREF_CLK>,
253               <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
254               <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
255      clock-names = "aux", "ref", "com_aux", "usb3_pipe";
256
257      power-domains = <&gcc USB30_PRIM_GDSC>;
258
259      resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
260               <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
261      reset-names = "phy", "common";
262
263      vdda-phy-supply = <&vreg_l9d>;
264      vdda-pll-supply = <&vreg_l4d>;
265
266      orientation-switch;
267
268      #clock-cells = <1>;
269      #phy-cells = <1>;
270
271      ports {
272          #address-cells = <1>;
273          #size-cells = <0>;
274
275          port@0 {
276              reg = <0>;
277
278              endpoint {
279                  remote-endpoint = <&typec_connector_ss>;
280              };
281          };
282
283          port@1 {
284              reg = <1>;
285
286              endpoint {
287                  remote-endpoint = <&dwc3_ss_out>;
288              };
289          };
290
291          port@2 {
292              reg = <2>;
293
294              endpoint {
295                  remote-endpoint = <&mdss_dp_out>;
296              };
297          };
298      };
299    };
300