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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
11 Available mpp pins/groups and functions:
16 name pins functions
20 mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
23 uart1(cts), lcd-spi(cs1), pmu*
26 mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu*
31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
[all …]
H A Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
16 Available mpp pins/groups and functions:
22 name pins functions
29 mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig)
[all …]
H A Dmarvell,armada-39x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
8 "marvell,88f6928-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
16 name pins functions
19 mpp1 1 gpio, ua0(txd)
22 mpp4 4 gpio, ua1(txd), ua0(rts), smi(mdc)
32 mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd)
36 mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck)
[all …]
H A Dmarvell,armada-370-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
14 name pins functions
17 mpp1 1 gpo, uart0(txd)
18 mpp2 2 gpio, i2c0(sck), uart0(txd)
20 mpp4 4 gpio, vdd(cpu-pd)
21 mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(sck), audio(mclk)
25 mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
[all …]
H A Dmarvell,armada-38x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
8 "marvell,88f6828-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
16 name pins functions
19 mpp1 1 gpio, ua0(txd)
22 mpp4 4 gpio, ge(mdc), ua1(txd), ua0(rts)
36 mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0)
43 mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)
[all …]
H A Dmarvell,armada-375-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6720-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
14 name pins functions
30 mpp14 14 gpio, i2c0(sda), uart1(txd)
32 mpp16 16 gpio, uart0(txd)
56 mpp40 40 gpio, uart1(txd)
76 mpp60 60 gpio, uart1(txd), led(c2)
H A Dmarvell,orion-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f5181-pinctrl",
8 "marvell,88f5181l-pinctrl",
9 "marvell,88f5182-pinctrl",
10 "marvell,88f5281-pinctrl"
12 - reg: two register areas, the first one describing the first two
16 Available mpp pins/groups and functions:
22 name pins functions
26 mpp2 2 gpio, pci(req3), pci-1(pme)
30 mpp6 6 gpio, pci(req5), pci-1(clk)
[all …]
H A Dmarvell,armada-98dx3236-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
8 - reg: register specifier of MPP registers
12 name pins functions
26 mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14)
32 mpp18 18 gpio, uart1(txd)
H A Dmarvell,armada-xp-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl"
9 - reg: register specifier of MPP registers
13 Available mpp pins/groups and functions:
19 name pins functions
50 mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk)
61 mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0),
63 mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
66 mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout),
[all …]
H A Dcanaan,k230-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k230-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ze Huang <18771902331@163.com>
13 The Canaan Kendryte K230 platform includes 64 IO pins, each capable of
15 performed on a per-pin basis.
19 const: canaan,k230-pinctrl
25 '-pins$':
33 '-cfg$':
[all …]
H A Draspberrypi,rp1-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/raspberrypi,rp1-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - A. della Porta <andrea.porta@suse.com>
14 sub-peripherals, a gpio/pinconf/mux controller whose 54 pins are grouped
20 const: raspberrypi,rp1-gpio
26 '#gpio-cells':
28 to specify the flags (see include/dt-bindings/gpio/gpio.h).
31 gpio-controller: true
[all …]
H A Dimg,pistachio-pinctrl.txt6 controller on Pistachio has 99 pins, 90 of which are MFIOs which can be
8 each. The GPIO banks are represented as sub-nodes of the pad controller node.
10 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
11 ../interrupt-controller/interrupts.txt for generic information regarding
15 --------------------------------------------
16 - compatible: "img,pistachio-system-pinctrl".
17 - reg: Address range of the pinctrl registers.
19 Required properties for GPIO bank sub-nodes:
20 --------------------------------------------
21 - interrupts: Interrupt line for the GPIO bank.
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Drzg2lc-smarc-pinfunction.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
16 /* SW8 should be at position 2->1 */
18 pinmux = <RZG2L_PORT_PINMUX(40, 0, 3)>, /* TxD */
24 /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
25 can1-stb-hog {
26 gpio-hog;
[all …]
H A Drzg2l-smarc-pinfunction.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
20 /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
21 can0-stb-hog {
22 gpio-hog;
24 output-low;
25 line-name = "can0_stb";
[all …]
H A Drzg2ul-smarc-pinfunction.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
21 can0-stb-hog {
22 gpio-hog;
24 output-low;
25 line-name = "can0_stb";
35 can1-stb-hog {
[all …]
H A Drzg3s-smarc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ SMARC Carrier-II Board.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
23 stdout-path = "serial3:115200n8";
27 compatible = "gpio-keys";
29 key-1 {
30 interrupts-extended = <&pinctrl RZG2L_GPIO(18, 0) IRQ_TYPE_EDGE_FALLING>;
33 wakeup-source;
[all …]
H A Dr9a07g044l2-remi-pi.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
17 model = "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI";
18 compatible = "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044";
36 stdout-path = "serial0:115200n8";
39 hdmi-out {
40 compatible = "hdmi-connector";
42 ddc-i2c-bus = <&i2c1>;
[all …]
H A Dr9a07g043-smarc-pmod.dtso1 // SPDX-License-Identifier: GPL-2.0
11 * +----------------------------+
17 * +----------------------------+
21 /dts-v1/;
24 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
27 can0-stb-hog {
31 can1-stb-hog {
35 sci0_pins: sci0-pins {
36 pinmux = <RZG2L_PORT_PINMUX(2, 2, 5)>, /* TxD */
42 pinctrl-0 = <&sci0_pins>;
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-href-family-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "ste-dbx5x0-pinctrl.dtsi"
19 pins = "GPIO216_AG12"; /* FRM */
23 pins = "GPIO218_AH11"; /* RXD */
27 pins =
28 "GPIO215_AH13", /* TXD */
37 * note that we have muxes the pins off the function here
41 pins = "GPIO218_AH11"; /* RXD */
45 pins = "GPIO215_AH13"; /* TXD */
49 pins = "GPIO217_AH12"; /* CLK */
[all …]
/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dcp110-system-controller.txt6 giving access to numerous features: clocks, pin-muxing and many other
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the CP110 system controller
18 -------
23 - a set of core clocks
24 - a set of gateable clocks
28 - The first cell must be 0 or 1. 0 for the core clocks and 1 for the
30 - The second cell identifies the particular core clock or gateable
34 - Core clocks
35 - 0 0 APLL
[all …]
H A Dap80x-system-controller.txt6 registers giving access to numerous features: clocks, pin-muxing and
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
18 -------
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be one of:
32 * "marvell,ap806-clock"
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dsama5d4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
9 #include <dt-bindings/clock/at91.h>
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/mfd/at91-usart.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
[all …]
H A Dlan966x-kontron-kswitch-d10-mmt.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
16 stdout-path = "serial0:115200n8";
19 gpio-restart {
20 compatible = "gpio-restart";
21 pinctrl-0 = <&reset_pins>;
22 pinctrl-names = "default";
29 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
33 pinctrl-0 = <&usart0_pins>;
[all …]
H A Dlan966x-pcb8309.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x_pcb8309.dts - Device Tree file for PCB8309
5 /dts-v1/;
7 #include "dt-bindings/phy/phy-lan966x-serdes.h"
10 model = "Microchip EVB - LAN9662";
11 compatible = "microchip,lan9662-pcb8309", "microchip,lan9662", "microchip,lan966";
20 stdout-path = "serial0:115200n8";
23 gpio-restart {
24 compatible = "gpio-restart";
29 i2c-mux {
[all …]
/linux/arch/powerpc/platforms/85xx/
H A Dtwr_p102x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
8 * TWR-P102x Board Setup
19 #include <asm/pci-bridge.h>
64 np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts"); in twr_p1025_setup_arch()
70 /* P1025 has pins muxed for QE and other functions. To in twr_p1025_setup_arch()
76 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | in twr_p1025_setup_arch()
87 * The UCC7 UART just can use RXD and TXD pins. in twr_p1025_setup_arch()
91 /* Drive PB29 to CPLD low - CPLD will then change in twr_p1025_setup_arch()
102 pr_info("TWR-P1025 board from Freescale Semiconductor\n"); in twr_p1025_setup_arch()
[all …]

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