| /freebsd/crypto/openssl/crypto/sha/asm/ |
| H A D | sha1-c64xplus.pl | 2 # Copyright 2012-2020 The OpenSSL Project Authors. All Rights Reserved.
21 # If compared to compiler-generated code with similar characteristics,
32 # service routines are expected to preserve it and for own well-being
41 ($TX0,$TX1,$TX2,$TX3) = map("B$_",(28..31));
68 || MVK -64,B0
70 || [A0] STW FP,*SP--[16] ; save frame pointer and alloca(64)
72 [A0] LDW *${CTX}[0],$A ; load A-E...
74 [A0] LDW *${CTX}[1],$B
82 LDNW *${INP}++,$TX1 ; pre-fetch input
83 NOP 1
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/net/can/ |
| H A D | nxp,sja1000.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
[all …]
|
| H A D | sja1000.txt | 5 - compatible : should be one of "nxp,sja1000", "technologic,sja1000".
7 - reg : should specify the chip select, address offset and size required
10 - interrupts: property with a value describing the interrupt source
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
16 should be performed on the device. Valid value is 1, 2 or 4.
18 Default to 1 (8 bits).
20 - nxp,external-clock-frequency : Frequency of the external oscillator
25 - nxp,tx-output-mode : operation mode of the TX output control logic:
26 <0x0> : bi-phase output mode
31 - nxp,tx-output-config : TX output pin configuration:
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/firmware/ |
| H A D | fsl,scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | amphion,vpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Min
[all...] |
| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | imx8-ss-vpu.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
8 #address-cells = <1>;
9 #size-cells = <1>;
12 power-domains = <&pd IMX_SC_R_VPU>;
16 compatible = "fsl,imx6sx-mu";
19 #mbox-cells = <2>;
20 power-domains = <&pd IMX_SC_R_VPU_MU_0>;
25 compatible = "fsl,imx6sx-mu";
28 #mbox-cells = <2>;
29 power-domains = <&pd IMX_SC_R_VPU_MU_1>;
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | onnn,nb7vpq904m.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ON Semiconductor Type-C DisplayPort ALT Mode Linear Redriver
10 - Neil Armstrong <neil.armstrong@linaro.org>
15 - onnn,nb7vpq904m
18 maxItems: 1
20 vcc-supply:
23 enable-gpios: true
25 retimer-switch:
[all …]
|
| H A D | am33xx-usb.txt | 3 - compatible: ti,am33xx-usb
4 - reg: offset and length of the usbss register sets
5 - ti,hwmods : must be "usb_otg_hs"
13 - compatible: ti,am335x-usb-ctrl-module
14 - reg: offset and length of the "USB control registers" in the "Control
17 - reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for
22 compatible: ti,am335x-usb-phy
25 reg-names: phy
31 - compatible: ti,musb-am33xx
32 - reg: offset and length of "USB Controller Registers", and offset and
[all …]
|
| H A D | da8xx-usb.txt | 3 For DA8xx/OMAP-L1x/AM17xx/AM18xx platforms.
7 - compatible : Should be set to "ti,da830-musb".
9 - reg: Offset and length of the USB controller register set.
11 - interrupts: The USB interrupt number.
13 - interrupt-names: Should be set to "mc".
15 - dr_mode: The USB operation mode. Should be one of "host", "peripheral" or "otg".
17 - phys: Phandle for the PHY device
19 - phy-names: Should be "usb-phy"
21 - dmas: specifies the dma channels
23 - dma-names: specifies the names of the channels. Use "rxN" for receive
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | nvidia,tegra210-admaif.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^admaif@[0-9a-f]*$"
26 - enum:
27 - nvidia,tegra210-admaif
28 - nvidia,tegra186-admaif
[all …]
|
| H A D | nvidia,tegra-audio-graph-card.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Sameer Pujar <spujar@nvidia.com>
19 - $ref: audio-graph.yaml#
24 - nvidia,tegra210-audio-graph-card
25 - nvidia,tegra186-audio-graph-card
30 clock-names:
[all …]
|
| H A D | renesas,rz-ssi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/renesas,rz-ss
[all...] |
| H A D | nvidia,tegra30-ahub.txt | 4 - compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114,
5 must contain "nvidia,tegra114-ahub". For Tegra124, must contain
6 "nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub",
8 - reg : Should contain the register physical address and length for each of
10 - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
11 - Tegra114 requires an additional entry, for the APBIF2 register block.
12 - interrupts : Should contain AHUB interrupt
13 - clocks : Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
15 - clock-names : Must include the following entries:
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/arm/freescale/ |
| H A D | fsl,scu.txt | 2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
28 rx, and 1 optional MU channel for general interrupt.
36 Channel 1 must be "tx1" or "rx1".
[all …]
|
| /freebsd/sys/contrib/device-tree/src/powerpc/ |
| H A D | tqm8xx.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <16>; // 16 bytes
32 i-cache-line-size = <16>; // 16 bytes
33 d-cache-size = <0x1000>; // L1, 4K
34 i-cache-size = <0x1000>; // L1, 4K
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm64/rockchip/ |
| H A D | rk3588-pinctrl.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 /omit-if-no-ref/
16 clk32k_out1: clk32k-out1 {
19 <2 RK_PC5 1 &pcfg_pull_none>;
25 /omit-if-no-ref/
26 eth0_pins: eth0-pins {
29 <2 RK_PC3 1 &pcfg_pull_none>;
35 /omit-if-no-ref/
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | omap-spi.txt | 4 - compatible :
5 - "ti,am654-mcspi" for AM654.
6 - "ti,omap2-mcspi" for OMAP2 & OMAP3.
7 - "ti,omap4-mcspi" for OMAP4+.
8 - ti,spi-num-cs : Number of chipselect supported by the instance.
9 - ti,hwmods: Name of the hwmod associated to the McSPI
10 - ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as
15 - dmas: List of DMA specifiers with the controller specific format
18 - dma-names: List of DMA request names. These strings correspond
19 1:1 with the DMA specifiers listed in dmas. The string naming
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | ti,k3-am654-cpsw-nuss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
22 Complex (UDMA-P) controller.
27 Support for Audio/Video Bridging (P802.1Qav/D6.0)
52 "#address-cells": true
53 "#size-cells": true
[all …]
|
| /freebsd/sys/dev/rtwn/rtl8192c/pci/ |
| H A D | r92ce_calib.c | 3 /*-
82 if (sc->ntxchains > 1) { in r92ce_iq_calib_chain()
84 /* IQ calibration settings for chain 1. */ in r92ce_iq_calib_chain()
85 rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22); in r92ce_iq_calib_chain()
86 rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22); in r92ce_iq_calib_chain()
87 rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102); in r92ce_iq_calib_chain()
88 rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202); in r92ce_iq_calib_chain()
98 } else { /* IQ calibration for chain 1. */ in r92ce_iq_calib_chain()
110 if (status & (1 << (28 + chain * 3))) in r92ce_iq_calib_chain()
115 tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(chain)), in r92ce_iq_calib_chain()
[all …]
|
| /freebsd/sys/dev/rtwn/rtl8188e/ |
| H A D | r88e_calib.c | 1 /*-
2 * Copyright (c) 2016-2019 Andriy Voskoboinyk <avos@FreeBSD.org>
75 rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(1), 0xf117b); in r88e_iq_calib_chain()
100 if (status & (1 << 28)) in r88e_iq_calib_chain()
106 tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(0)), in r88e_iq_calib_chain()
108 if (tx[0] == 0x142 || tx[1] == 0x042) in r88e_iq_calib_chain()
111 rtwn_bb_write(sc, R92C_TX_IQK, 0x80007c00 | (tx[0] << 16) | tx[1]); in r88e_iq_calib_chain()
118 rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(1), 0xf7ffa); in r88e_iq_calib_chain()
142 if (status & (1 << 27)) in r88e_iq_calib_chain()
143 return (1); /* Rx failed. */ in r88e_iq_calib_chain()
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | qcom,edp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
20 - qcom,sc7280-edp-phy
21 - qcom,sc8180x-edp-phy
22 - qcom,sc8280xp-dp-phy
23 - qcom,sc8280xp-edp-phy
27 - description: PHY base register block
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | omap2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/omap.h>
15 interrupt-parent = <&intc>;
16 #address-cells = <1>;
17 #size-cells = <1>;
29 #address-cells = <0>;
[all …]
|
| H A D | dm814x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/bus/ti-sysc.h>
4 #include <dt-bindings/clock/dm814.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/dm814x.h>
10 interrupt-parent = <&intc>;
11 #address-cells = <1>;
12 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
[all …]
|
| H A D | dm816x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/bus/ti-sysc.h>
4 #include <dt-bindings/clock/dm816.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/omap.h>
10 interrupt-parent = <&intc>;
11 #address-cells = <1>;
12 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
[all …]
|
| /freebsd/sys/dev/rtwn/rtl8192c/ |
| H A D | r92c_calib.c | 3 /*-
82 if (sc->ntxchains > 1) { in r92c_iq_calib_chain()
84 /* IQ calibration settings for chain 1. */ in r92c_iq_calib_chain()
85 rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22); in r92c_iq_calib_chain()
86 rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22); in r92c_iq_calib_chain()
87 rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102); in r92c_iq_calib_chain()
88 rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202); in r92c_iq_calib_chain()
98 } else { /* IQ calibration for chain 1. */ in r92c_iq_calib_chain()
110 if (status & (1 << (28 + chain * 3))) in r92c_iq_calib_chain()
115 tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(chain)), in r92c_iq_calib_chain()
[all …]
|