Lines Matching +full:tx1 +full:- +full:1
3 /*-
82 if (sc->ntxchains > 1) { in r92ce_iq_calib_chain()
84 /* IQ calibration settings for chain 1. */ in r92ce_iq_calib_chain()
85 rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22); in r92ce_iq_calib_chain()
86 rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22); in r92ce_iq_calib_chain()
87 rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102); in r92ce_iq_calib_chain()
88 rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202); in r92ce_iq_calib_chain()
98 } else { /* IQ calibration for chain 1. */ in r92ce_iq_calib_chain()
110 if (status & (1 << (28 + chain * 3))) in r92ce_iq_calib_chain()
115 tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(chain)), in r92ce_iq_calib_chain()
117 if (tx[0] == 0x142 || tx[1] == 0x042) in r92ce_iq_calib_chain()
120 if (status & (1 << (27 + chain * 3))) in r92ce_iq_calib_chain()
121 return (1); /* Rx failed. */ in r92ce_iq_calib_chain()
125 rx[1] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(chain)), in r92ce_iq_calib_chain()
127 if (rx[0] == 0x132 || rx[1] == 0x036) in r92ce_iq_calib_chain()
128 return (1); /* Rx failed. */ in r92ce_iq_calib_chain()
149 vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]); in r92ce_iq_calib_run()
151 vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE); in r92ce_iq_calib_run()
152 vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0)); in r92ce_iq_calib_run()
153 vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1)); in r92ce_iq_calib_run()
154 vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG); in r92ce_iq_calib_run()
157 if (sc->ntxchains == 1) { in r92ce_iq_calib_run()
159 for (i = 1; i < nitems(reg_adda); i++) in r92ce_iq_calib_run()
170 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), in r92ce_iq_calib_run()
175 vals->ofdm0_trxpathena = in r92ce_iq_calib_run()
177 vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); in r92ce_iq_calib_run()
178 vals->fpga0_rfifacesw1 = in r92ce_iq_calib_run()
179 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); in r92ce_iq_calib_run()
184 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000); in r92ce_iq_calib_run()
185 if (sc->ntxchains > 1) { in r92ce_iq_calib_run()
187 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000); in r92ce_iq_calib_run()
193 vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN); in r92ce_iq_calib_run()
194 rtwn_write_1(sc, R92C_BCN_CTRL(1), in r92ce_iq_calib_run()
195 vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN); in r92ce_iq_calib_run()
197 vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT); in r92ce_iq_calib_run()
200 if (sc->ntxchains > 1) in r92ce_iq_calib_run()
209 for (chain = 0; chain < sc->ntxchains; chain++) { in r92ce_iq_calib_run()
216 /* Enable chain 1. */ in r92ce_iq_calib_run()
232 tx[chain][1] = 0xff; in r92ce_iq_calib_run()
234 rx[chain][1] = 0xff; in r92ce_iq_calib_run()
235 } else if (ret == 1) { in r92ce_iq_calib_run()
240 rx[chain][1] = 0xff; in r92ce_iq_calib_run()
250 "tx[1] 0x%x, rx[0] 0x%x, rx[1] 0x%x\n", __func__, n, chain, in r92ce_iq_calib_run()
251 tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1]); in r92ce_iq_calib_run()
255 vals->ofdm0_trxpathena); in r92ce_iq_calib_run()
256 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), in r92ce_iq_calib_run()
257 vals->fpga0_rfifacesw1); in r92ce_iq_calib_run()
258 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar); in r92ce_iq_calib_run()
262 if (sc->ntxchains > 1) in r92ce_iq_calib_run()
263 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3); in r92ce_iq_calib_run()
268 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1); in r92ce_iq_calib_run()
272 rtwn_bb_write(sc, reg_adda[i], vals->adda[i]); in r92ce_iq_calib_run()
274 rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause); in r92ce_iq_calib_run()
275 rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]); in r92ce_iq_calib_run()
276 rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]); in r92ce_iq_calib_run()
277 rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg); in r92ce_iq_calib_run()
283 r92ce_iq_calib_compare_results(struct rtwn_softc *sc, uint16_t tx1[2][2], in r92ce_iq_calib_compare_results()
288 tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0; in r92ce_iq_calib_compare_results()
289 for (chain = 0; chain < sc->ntxchains; chain++) { in r92ce_iq_calib_compare_results()
291 if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff || in r92ce_iq_calib_compare_results()
295 tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <= in r92ce_iq_calib_compare_results()
298 rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <= in r92ce_iq_calib_compare_results()
303 if (sc->ntxchains > 1) in r92ce_iq_calib_compare_results()
304 return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]); in r92ce_iq_calib_compare_results()
317 if (tx[0] == 0xff || tx[1] == 0xff) in r92ce_iq_calib_write_results()
330 y = tx[1]; in r92ce_iq_calib_write_results()
341 if (rx[0] == 0xff || rx[1] == 0xff) in r92ce_iq_calib_write_results()
347 (rx[1] & 0x3f) << 10); in r92ce_iq_calib_write_results()
351 (rx[1] & 0x3c0) << 22); in r92ce_iq_calib_write_results()
354 (rx[1] & 0x3c0) << 6); in r92ce_iq_calib_write_results()
374 valid = r92ce_iq_calib_compare_results(sc, tx[n - 1], in r92ce_iq_calib()
375 rx[n - 1], tx[n], rx[n]); in r92ce_iq_calib()
382 if (sc->ntxchains > 1) in r92ce_iq_calib()
383 r92ce_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1); in r92ce_iq_calib()