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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
35 - const: snps,dwc3
[all …]
H A Ddwc3.txt3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
[all …]
H A Dci-hdrc-usb2.txt4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
13 "fsl,imx7ulp-usb"
[all …]
H A Dchipidea,usb2-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
25 clock-names:
31 power-domains:
37 reset-names:
40 "#reset-cells":
45 itc-setting:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
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H A Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Drenesas,nbpfaxi.txt1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
28 than using the maximum burst size allowed by the hardware's buffer size.
29 - max-burst-mem-write: limit burst size for memory writes
31 than using the maximum burst size allowed by the hardware's buffer size.
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
[all …]
H A Dimg-mdc-dma.txt1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clock/clock-bindings.txt for details.
9 - clock-names: Must include the following entries:
10 - sys: MDC system interface clock.
11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
[all …]
/freebsd/sys/dev/mlx5/mlx5_en/
H A Den_rl.h1 /*-
50 #define MLX5E_RL_WORKER_LOCK(rlw) mtx_lock(&(rlw)->mtx)
51 #define MLX5E_RL_WORKER_UNLOCK(rlw) mtx_unlock(&(rlw)->mtx)
53 #define MLX5E_RL_RLOCK(rl) sx_slock(&(rl)->rl_sxlock)
54 #define MLX5E_RL_RUNLOCK(rl) sx_sunlock(&(rl)->rl_sxlock)
56 #define MLX5E_RL_WLOCK(rl) sx_xlock(&(rl)->rl_sxlock)
57 #define MLX5E_RL_WUNLOCK(rl) sx_xunlock(&(rl)->rl_sxlock)
61 m(+1, u64, tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining TX packets") \
62 m(+1, u64, tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of TX packets to join") \
64 m(+1, u64, tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \
[all …]
H A Dmlx5_en_rl.c1 /*-
2 * Copyright (c) 2016-2020 Mellanox Technologies. All rights reserved.
57 void *sqc = param->sqc; in mlx5e_rl_build_sq_param()
59 uint8_t log_sq_size = order_base_2(rl->param.tx_queue_size); in mlx5e_rl_build_sq_param()
63 MLX5_SET(wq, wq, pd, rl->priv->pdn); in mlx5e_rl_build_sq_param()
65 param->wq.linear = 1; in mlx5e_rl_build_sq_param()
72 void *cqc = param->cqc; in mlx5e_rl_build_cq_param()
73 uint8_t log_sq_size = order_base_2(rl->param.tx_queue_size); in mlx5e_rl_build_cq_param()
76 MLX5_SET(cqc, cqc, cq_period, rl->param.tx_coalesce_usecs); in mlx5e_rl_build_cq_param()
77 MLX5_SET(cqc, cqc, cq_max_count, rl->param.tx_coalesce_pkts); in mlx5e_rl_build_cq_param()
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_freebsd_inc.h12 #define AH_NEED_TX_DATA_SWAP 0 /* TX descriptor swap? */
13 #define AH_NEED_RX_DATA_SWAP 0 /* TX descriptor swap? */
59 #define OS_ATOMIC_DEC(a) (*a)--
84 * Green Tx, Based on different RSSI of Received Beacon thresholds,
85 * using different tx power by modified register tx power related values.
99 u_int32_t rp_numpulses ; /* Num of pulses in radar burst */
101 u_int32_t rp_pulsefreq; /* Frequency of pulses in burst */
102 u_int32_t rp_max_pulsefreq; /* Frequency of pulses in burst */
105 matched filter (single-sided) in usecs */
110 u_int32_t rp_maxdur; /* Max pusle duration to be considered for
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 * pre-existing /chosen node to be available to insert the
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
[all …]
H A Dimx6sl.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6sl-pinfunc.h"
7 #include <dt-bindings/clock/imx6sl-clock.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
50 #address-cells = <1>;
51 #size-cells = <0>;
54 compatible = "arm,cortex-a9";
[all …]
H A Dimx6sx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
60 #address-cells = <1>;
[all …]
H A Dimx6ul.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6ul-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6ul-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
57 #address-cells = <1>;
[all …]
H A Dimx6sll.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright 2017-2018 NXP.
8 #include <dt-bindings/clock/imx6sll-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx6sll-pinfunc.h"
14 #address-cells = <1>;
15 #size-cells = <1>;
46 #address-cells = <1>;
47 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_udma_config.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
81 uint8_t burst; member
94 al_bool break_on_max_boundary; /* Data read break on max boundary */
95 uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */
107 al_bool break_on_max_boundary; /* Data read break on max boundary */
108 uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */
123 /** M2S max packet size configuration */
135 uint8_t max_desc_per_packet; /* max number of descriptors to
[all …]
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Dlocation.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2015-2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2022 Intel Corporation
5 * Copyright (C) 2024-2025 Intel Corporation
16 * enum iwl_location_subcmd_ids - location group command IDs
91 * struct iwl_tof_config_cmd - ToF configuration
93 * @one_sided_disabled: indicates if one-sided is disabled (or not)
105 * enum iwl_tof_bandwidth - values for iwl_tof_range_req_ap_entry.bandwidth
106 * @IWL_TOF_BW_20_LEGACY: 20 MHz non-HT
123 * enum iwl_tof_algo_type - Algorithym type for range measurement request
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zc1232-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
27 stdout-path = "serial0:115200n8";
43 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
44 #address-cells = <1>;
45 #size-cells = <1>;
47 spi-tx-bus-width = <4>;
[all …]
H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
[all …]
H A Dzynqmp-zcu104-revC.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
[all …]
/freebsd/sys/dev/spibus/controller/allwinner/
H A Daw_spi.c1 /*-
61 #define AW_SPI_TCR_DDB (1 << 9) /* Dummy Burst Type */
87 #define AW_SPI_FCR_TX_RST (1 << 31) /* Reset TX FIFO */
88 #define AW_SPI_FCR_TX_TRIG_MASK 0xFF0000 /* TX FIFO Trigger level */
115 #define AW_SPI_MBC 0x30 /* Burst Counter Register */
117 #define AW_SPI_BCC 0x38 /* Burst Control Register */
119 #define AW_SPI_TXD 0x200 /* TX Data Register */
126 { "allwinner,sun8i-h3-spi", 1 },
133 { -1, 0 }
156 #define AW_SPI_LOCK(sc) mtx_lock(&(sc)->mtx)
[all …]
/freebsd/sys/dev/ath/
H A Dif_ath_tx_ht.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
109 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
111 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
170 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
178 { 104, 216 }, // 3: 16-QAM 1/2
179 { 156, 324 }, // 4: 16-QAM 3/4
180 { 208, 432 }, // 5: 64-QAM 2/3
181 { 234, 486 }, // 6: 64-QAM 3/4
182 { 260, 540 }, // 7: 64-QAM 5/6
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam335x-nano.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/
5 /dts-v1/;
15 cpu0-supply = <&dcdc2_reg>;
25 compatible = "gpio-leds";
30 default-state = "off";
36 pinctrl-names = "default";
37 pinctrl-0 = <&misc_pins>;
39 misc_pins: misc-pins {
40 pinctrl-single,pins = <
[all …]
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3xxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
37 compatible = "fixed-clock";
38 clock-frequency = <24000000>;
39 #clock-cells = <0>;
[all …]

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