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/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
[all …]
/linux/drivers/net/ethernet/sun/
H A Dsunbmac.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-mem size (64K) */
43 #define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */
45 #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
50 #define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */
51 #define CREG_TXRBUFPTR 0x2cUL /* Local memory tx read ptr */
59 #define CREG_STAT_TXDERROR 0x00080000 /* TX Descriptor is bogus */
76 #define CREG_QMASK_TXLERR 0x00040000 /* TX late error */
77 #define CREG_QMASK_TXPERR 0x00020000 /* TX parity error */
78 #define CREG_QMASK_TXSERR 0x00010000 /* TX sbus error ack */
[all …]
H A Dsunhme.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
39 #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
40 #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
41 #define GREG_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
42 #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
45 #define GREG_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
46 #define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
47 #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
48 #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
[all …]
/linux/arch/powerpc/boot/dts/
H A Deiger.dts11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
[all …]
H A Darches.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
24 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by U-Boot */
42 timebase-frequency = <0>; /* Filled in by U-Boot */
43 i-cache-line-size = <32>;
[all …]
H A Dtaishan.dts13 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <1>;
20 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <800000000>; // 800MHz
38 timebase-frequency = <0>; // Filled in by zImage
39 i-cache-line-size = <50>;
40 d-cache-line-size = <50>;
[all …]
H A Dfsp2.dts12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by cuboot */
36 timebase-frequency = <0>; /* Filled in by cuboot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
[all …]
H A Dsam440ep.dts16 /dts-v1/;
19 #address-cells = <2>;
20 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
45 i-cache-size = <32768>;
[all …]
H A Dbamboo.dts14 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <1>;
21 dcr-parent = <&{/cpus/cpu@0}>;
33 #address-cells = <1>;
34 #size-cells = <0>;
40 clock-frequency = <0>; /* Filled in by zImage */
41 timebase-frequency = <0>; /* Filled in by zImage */
42 i-cache-line-size = <32>;
43 d-cache-line-size = <32>;
[all …]
H A Dglacier.dts4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
[all …]
H A Drainier.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
[all …]
H A Dyosemite.dts12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <0>; /* Filled in by zImage */
39 timebase-frequency = <0>; /* Filled in by zImage */
40 i-cache-line-size = <32>;
41 d-cache-line-size = <32>;
[all …]
H A Debony.dts14 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <1>;
21 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <0>; // Filled in by zImage
39 timebase-frequency = <0>; // Filled in by zImage
40 i-cache-line-size = <32>;
41 d-cache-line-size = <32>;
[all …]
H A Dac14xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #address-cells = <1>;
15 #size-cells = <1>;
26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
49 compatible = "cfi-flash";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 bank-width = <2>;
[all …]
H A Dsequoia.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
[all …]
/linux/drivers/net/can/m_can/
H A Dm_can.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
8 * https://github.com/linux-can/can-doc/tree/master/m_can
226 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
230 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
237 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
243 /* Tx Buffer Configuration (TXBC) */
247 /* Tx FIFO/Queue Status (TXFQS) */
253 /* Tx Buffer Element Size Configuration (TXESC) */
257 /* Tx Event FIFO Configuration (TXEFC) */
[all …]
/linux/drivers/i2c/busses/
H A Di2c-pnx.c7 * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
36 int order; /* RX Bytes to order via TX */
82 #define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
83 #define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
84 #define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
85 #define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
86 #define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
87 #define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
88 #define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
89 #define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
[all …]
H A Di2c-bcm-iproc.c1 // SPDX-License-Identifier: GPL-2.0-only
138 #define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1)
155 * running for less time, max slave read per tasklet is set to 10 bytes.
233 if (iproc_i2c->idm_base) { in iproc_i2c_rd_reg()
234 spin_lock_irqsave(&iproc_i2c->idm_lock, flags); in iproc_i2c_rd_reg()
235 writel(iproc_i2c->ape_addr_mask, in iproc_i2c_rd_reg()
236 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); in iproc_i2c_rd_reg()
237 val = readl(iproc_i2c->base + offset); in iproc_i2c_rd_reg()
238 spin_unlock_irqrestore(&iproc_i2c->idm_lock, flags); in iproc_i2c_rd_reg()
240 val = readl(iproc_i2c->base + offset); in iproc_i2c_rd_reg()
[all …]
/linux/drivers/usb/gadget/udc/
H A Dsnps_udc_core.c1 // SPDX-License-Identifier: GPL-2.0+
3 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
5 * Copyright (C) 2005-2007 AMD (https://www.amd.com)
63 * slave mode: pending bytes in rx fifo after nyet,
76 /* set_rde -- Is used to control enabling of RX DMA. Problem is
79 * when OUT data reaches the fifo but no request was queued yet.
82 * in the FIFO (important for not blocking control traffic).
85 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
87 * set_rde 1 == timer function will look whether FIFO has data
90 static int set_rde = -1;
[all …]
/linux/drivers/spi/
H A Dspi-hisi-kunpeng.c1 // SPDX-License-Identifier: GPL-2.0-only
8 // This code is based on spi-dw-core.c.
26 #define HISI_SPI_FIFOC 0x0c /* fifo level control register */
57 #define SR_TXE BIT(0) /* Transmit FIFO empty */
58 #define SR_TXNF BIT(1) /* Transmit FIFO not full */
59 #define SR_RXNE BIT(2) /* Receive FIFO not empty */
60 #define SR_RXF BIT(3) /* Receive FIFO full */
129 u32 fifo_len; /* depth of the FIFO buffer */
132 const void *tx; member
167 host = container_of(hs->dev, struct spi_controller, dev); in hisi_spi_debugfs_init()
[all …]
H A Dspi-fsl-espi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
27 #define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/
28 #define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/
62 #define SPIE_TXE BIT(15) /* TX FIFO empty */
63 #define SPIE_DON BIT(14) /* TX done */
64 #define SPIE_RXT BIT(13) /* RX FIFO threshold */
65 #define SPIE_RXF BIT(12) /* RX FIFO full */
66 #define SPIE_TXT BIT(11) /* TX FIFO threshold*/
67 #define SPIE_RNE BIT(9) /* RX FIFO not empty */
68 #define SPIE_TNF BIT(8) /* TX FIFO not full */
[all …]
/linux/arch/nios2/boot/dts/
H A D10m50_devboard.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
10 compatible = "altr,niosii-max10";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "altr,nios2-1.1";
22 interrupt-controller;
23 #interrupt-cells = <1>;
[all …]
H A D3c120_devboard.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "altr,nios2-1.0";
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 clock-frequency = <125000000>;
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dtx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 * enum iwl_tx_flags - bitmasks for tx_flags in TX command
12 * @TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
13 * @TX_CMD_FLG_WRITE_TX_POWER: update current tx power value in the mgmt frame
15 * @TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
16 * Otherwise, use rate_n_flags from the TX command
28 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
29 * @TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
[all …]

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