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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dvideo-interfaces.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interface
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H A Dti,omap3isp.txt4 The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
9 compatible : must contain "ti,omap3-isp"
11 reg : the two registers sets (physical address and length) for the
17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
19 ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
20 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
21 #clock-cells : Must be 1 --- the ISP provides two external clocks,
24 clock bindings in ../clock/clock-bindings.txt.
27 ---------------------
30 video-interfaces.txt in the same directory.
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/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dimx219.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
12 description: |-
13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
16 Image data is sent through MIPI CSI-2, which is configured as either 2 or
30 VDIG-supply:
34 VANA-supply:
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H A Dthine,thp7312.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Elder <paul.elder@@ideasonboard.com>
17 MIPI CSI-2 and parallel interfaces. It can also output on either MIPI CSI-2
23 - $ref: /schemas/media/video-interface-devices.yaml#
36 thine,boot-mode:
43 0 is for the SPI/2-wire slave boot, 1 is for the SPI master boot (from
46 reset-gpios:
52 vddcore-supply:
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H A Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
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H A Dst,st-mipid02.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid0
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H A Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
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H A Dadv748x.txt4 HDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB
9 - compatible: Must contain one of the following
10 - "adi,adv7481" for the ADV7481
11 - "adi,adv7482" for the ADV7482
13 - reg: I2C slave addresses
14 The ADV748x has up to twelve 256-byte maps that can be accessed via the
21 - interrupt-names: Should specify the interrupts as "intrq1", "intrq2" and/or
24 - interrupts: Specify the interrupt lines for the ADV748x
25 - reg-names : Names of maps with programmable addresses.
26 It shall contain all maps needing a non-default address.
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/freebsd/sys/contrib/libsodium/src/libsodium/crypto_pwhash/argon2/
H A Dargon2-core.h35 /* Number of pseudo-random values generated by one call to Blake in Argon2i
40 /* Pre-hashing digest length and its extension*/
49 * Structure for the (1KB) memory block implemented as 128 64-bit words.
69 memset(b->v, in, sizeof(b->v)); in init_block_value()
76 memcpy(dst->v, src->v, sizeof(uint64_t) * ARGON2_QWORDS_IN_BLOCK); in copy_block()
85 dst->v[i] ^= src->v[i]; in xor_block()
115 uint32_t lane; member
130 * Computes absolute position of reference block in the lane following a skewed
131 * distribution and using a pseudo-random value as input
134 * @param pseudo_rand 32-bit pseudo-random value used to determine the position
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H A Dargon2-fill-block-avx2.c18 #include "argon2-core.h"
41 # include "blamka-round-avx2.h"
111 input_block.v[0] = position->pass; in generate_addresses()
112 input_block.v[1] = position->lane; in generate_addresses()
113 input_block.v[2] = position->slice; in generate_addresses()
114 input_block.v[3] = instance->memory_blocks; in generate_addresses()
115 input_block.v[4] = instance->passes; in generate_addresses()
116 input_block.v[5] = instance->type; in generate_addresses()
118 for (i = 0; i < instance->segment_length; ++i) { in generate_addresses()
120 /* Temporary zero-initialized blocks */ in generate_addresses()
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H A Dargon2-fill-block-avx512f.c18 #include "argon2-core.h"
42 # include "blamka-round-avx512f.h"
116 input_block.v[0] = position->pass; in generate_addresses()
117 input_block.v[1] = position->lane; in generate_addresses()
118 input_block.v[2] = position->slice; in generate_addresses()
119 input_block.v[3] = instance->memory_blocks; in generate_addresses()
120 input_block.v[4] = instance->passes; in generate_addresses()
121 input_block.v[5] = instance->type; in generate_addresses()
123 for (i = 0; i < instance->segment_length; ++i) { in generate_addresses()
125 /* Temporary zero-initialized blocks */ in generate_addresses()
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H A Dargon2-fill-block-ssse3.c18 #include "argon2-core.h"
36 # include "blamka-round-ssse3.h"
110 input_block.v[0] = position->pass; in generate_addresses()
111 input_block.v[1] = position->lane; in generate_addresses()
112 input_block.v[2] = position->slice; in generate_addresses()
113 input_block.v[3] = instance->memory_blocks; in generate_addresses()
114 input_block.v[4] = instance->passes; in generate_addresses()
115 input_block.v[5] = instance->type; in generate_addresses()
117 for (i = 0; i < instance->segment_length; ++i) { in generate_addresses()
119 /* Temporary zero-initialized blocks */ in generate_addresses()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp1 //=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // The Cortex-A15 processor employs a tracking scheme in its register renaming
10 // in order to process each instruction's micro-ops speculatively and
11 // out-of-order with appropriate forwarding. The ARM architecture allows VFP
12 // instructions to read and write 32-bit S-registers. Each S-register
13 // corresponds to one half (upper or lower) of an overlaid 64-bit D-register.
17 // direct patterns, specifically around when one micro-op reads a D-register
18 // operand that has recently been written as one or more S-register results.
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H A DARMInstrNEON.td1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific Operands.
16 //===----------------------------------------------------------------------===//
131 // Register list of two sequential D registers.
158 // Register list of two D registers spaced by 2 (two sequential Q registers).
195 // Register list of two D registers, with "all lanes" subscripting.
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/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_kr.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
38 * Ethernet KR auto-neg and link-training driver API
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
59 /* AN (Auto-negotiation) Advertisement Registers */
77 * Two devices must have a different nonce for autonegotiation to
154 * @param lane lane number
160 enum al_eth_an_lt_lane lane,
167 * @param lane lane number
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/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dimx-sata.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawn.guo@linaro.org>
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
22 - fsl,imx8qm-ahci
33 - description: sata clock
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/freebsd/sys/contrib/openzfs/module/zfs/
H A Dzio_inject.c9 * or https://opensource.org/licenses/CDDL-1.0.
25 * Copyright (c) 2024-2025, Klara, Inc.
138 if (zb->zb_objset == DMU_META_OBJSET && in zio_match_handler()
139 record->zi_objset == DMU_META_OBJSET && in zio_match_handler()
140 record->zi_object == DMU_META_DNODE_OBJECT) { in zio_match_handler()
141 if (record->zi_type == DMU_OT_NONE || in zio_match_handler()
142 type == record->zi_type) in zio_match_handler()
150 if (zb->zb_objset == record->zi_objset && in zio_match_handler()
151 zb->zb_objec in zio_match_handler()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp1 //===- X86InterleavedAccess.cpp -------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 /// optimization generating X86-specific instructions/intrinsics for
14 //===----------------------------------------------------------------------===//
43 /// X86-specific instructions/intrinsics.
50 /// Reference to the wide-load instruction of an interleaved access
57 /// Reference to the starting index of each user-shuffle.
71 /// sub vectors of type \p T. Returns the sub-vectors in \p DecomposedVectors.
76 /// returns the transposed-vectors in \p TransposedVectors.
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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DLaneBitmask.h1 //===- llvm/MC/LaneBitmask.h ------------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 /// A lane mask is a bitmask representing the covering of a register with
13 /// sub-registers.
15 /// This is typically used to track liveness at sub-register granularity.
16 /// Lane masks for sub-register indices are similar to register units for
17 /// physical registers. The individual bits in a lane mask can't be assigned
18 /// any specific meaning. They can be used to check if two sub-register
83 static constexpr LaneBitmask getLane(unsigned Lane) { in getLane()
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/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dti,sn65dsi86.txt2 --------------------------------
8 - compatible: Must be "ti,sn65dsi86"
9 - reg: i2c address of the chip, 0x2d as per datasheet
10 - enable-gpios: gpio specification for bridge_en pin (active high)
12 - vccio-supply: A 1.8V supply that powers up the digital IOs.
13 - vpll-supply: A 1.8V supply that powers up the displayport PLL.
14 - vcca-supply: A 1.2V supply that powers up the analog circuits.
15 - vcc-supply: A 1.2V supply that powers up the digital core.
18 - interrupts-extended: Specifier for the SN65DSI86 interrupt line.
20 - gpio-controller: Marks the device has a GPIO controller.
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dti-pci.txt4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../snps,dw-pcie.yaml
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/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp-mv78460.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
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/freebsd/sys/contrib/openzfs/man/man8/
H A Dzinject.89 .\" or https://opensource.org/licenses/CDDL-1.0.
24 .\" lint-ok: WARNING: sections out of conventional order: Sh SYNOPSIS
40 .Bl -tag -width Ds
85 For example, with a single lane delay of 10 ms
94 Similarly, if a delay of 10 ms is specified to have two
98 two requests at a time, each with a minimum latency of 10 ms.
99 So, if two requests are submitted every 10 ms, then
100 the average latency will be 10 ms; but if more than two
105 So two invocation
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/freebsd/contrib/arm-optimized-routines/math/aarch64/experimental/advsimd/
H A Derfinvf_5u.c2 * Single-precision inverse error function (AdvSIMD variant).
4 * Copyright (c) 2023-2024, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
18 formats to allow for table-based (vector-to-vector) lookup.
20 Plo is first two coefficients of P_10 and P_29 interleaved.
36 .P29_3 = V4 (0x1.b13626p-2),
37 .tailshift = V4 (-0.87890625),
38 .Plo = { -0x1.a31268p+3, -0x1.fc0252p-4, 0x1.ac9048p+4, 0x1.119d44p+0 },
39 .PQ = { -0x1.293ff6p+3, -0x1.f59ee2p+0, -0x1.8265eep+3, -0x1.69952p-4 },
40 .Qhi = { 0x1.ef5eaep+4, 0x1.c7b7d2p-1, -0x1.12665p+4, -0x1.167d7p+1 },
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