Lines Matching +full:two +full:- +full:lane

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawn.guo@linaro.org>
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
22 - fsl,imx8qm-ahci
33 - description: sata clock
34 - description: sata reference clock
35 - description: ahb clock
37 clock-names:
40 - const: sata
41 - const: sata_ref
42 - const: ahb
44 fsl,transmit-level-mV:
48 fsl,transmit-boost-mdB:
50 description: transmit boost level, in milli-decibels.
52 fsl,transmit-atten-16ths:
56 fsl,receive-eq-mdB:
58 description: receive equalisation, in milli-decibels.
60 fsl,no-spread-spectrum:
62 description: if present, disable spread-spectrum clocking on the SATA link.
66 - description: phandle to SATA PHY.
67 Since "REXT" pin is only present for first lane of i.MX8QM PHY, it's
68 calibration result will be stored, passed through second lane, and
69 shared with all three lanes PHY. The first two lanes PHY are used as
70 calibration PHYs, although only the third lane PHY is used by SATA.
71 - description: phandle to the first lane PHY of i.MX8QM.
72 - description: phandle to the second lane PHY of i.MX8QM.
74 phy-names:
76 - const: sata-phy
77 - const: cali-phy0
78 - const: cali-phy1
80 power-domains:
84 - compatible
85 - reg
86 - interrupts
87 - clocks
88 - clock-names
91 - if:
96 - fsl,imx53-ahci
97 - fsl,imx6q-ahci
98 - fsl,imx6qp-ahci
101 clock-names:
104 - if:
109 - fsl,imx8qm-ahci
112 clock-names:
118 - |
119 #include <dt-bindings/clock/imx6qdl-clock.h>
120 #include <dt-bindings/interrupt-controller/arm-gic.h>
123 compatible = "fsl,imx6q-ahci";
129 clock-names = "sata", "sata_ref", "ahb";