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Searched full:trbe (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/hwtracing/coresight/
H A Dcoresight-trbe.c3 * This driver enables Trace Buffer Extension (TRBE) as a per-cpu coresight
24 #include "coresight-trbe.h"
32 * data which could not be decoded. TRBE doesn't support
65 /* The base programmed into the TRBE */
76 * TRBE erratum list
80 * to the affected CPUs inside the TRBE driver, we need to know if
82 * work arounds, TRBE driver needs to check multiple times during
85 * We keep a set of the affected errata in trbe_cpudata, per TRBE.
88 * TRBE erratum. We map the given cpucap into a TRBE internal number
120 * struct trbe_cpudata: TRBE instance specific data
[all …]
H A Dcoresight-trbe.h4 * Trace Buffer Extension (TRBE) driver in the coresight framework.
25 unsigned int trbe = cpuid_feature_extract_unsigned_field(aa64dfr0, in is_trbe_available() local
28 return trbe >= ID_AA64DFR0_EL1_TraceBuffer_IMP; in is_trbe_available()
H A Dcoresight-kunit-tests.c37 * a TRBE sink if one is registered. in test_default_sink()
/linux/Documentation/trace/coresight/
H A Dcoresight-trbe.rst4 Trace Buffer Extension (TRBE).
13 Trace Buffer Extension (TRBE) is a percpu hardware which captures in system
18 The TRBE is not compliant to CoreSight architecture specifications, but is
25 The TRBE devices appear on the existing coresight bus alongside the other
31 The ``trbe<N>`` named TRBEs are associated with a CPU.::
37 * ``align``: TRBE write pointer alignment
38 * ``flag``: TRBE updates memory with access and dirty flags
/linux/Documentation/devicetree/bindings/arm/
H A Darm,trace-buffer-extension.yaml14 Arm Trace Buffer Extension (TRBE) is a per CPU component
22 const: trbe
31 TRBE is only supported on a subset of the CPUs, please consult
46 trbe {
/linux/arch/arm64/
H A DKconfig871 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
889 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
943 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
951 for TRBE. Under some conditions, the TRBE might generate a write to the next
952 virtually addressed page following the last page of the TRBE address space
956 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
961 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
969 for TRBE. Under some conditions, the TRBE might generate a write to the next
970 virtually addressed page following the last page of the TRBE address space
974 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
[all …]
/linux/arch/arm64/kvm/hyp/nvhe/
H A Ddebug-sr.c76 /* Unsupported with TRBE so disable */ in __trace_switch_to_guest()
H A Dswitch.c281 * above disabling of BRBE, SPE and TRBE. in __kvm_vcpu_run()
/linux/arch/arm64/kernel/
H A Dhyp-stub.S120 // Use EL2 translations for SPE & TRBE and disable access from EL1
H A Dcpu_errata.c773 * The erratum work around is handled within the TRBE
/linux/arch/arm64/kvm/
H A Ddebug.c97 /* Force disable trace in protected mode in case of no TRBE */ in kvm_init_host_debug_data()
H A Dconfig.c300 * Revists this if KVM ever supports both MPAM and TRBE -- in feat_trbe_mpam()
/linux/arch/arm64/boot/dts/arm/
H A Dfvp-base-revc.dts323 trbe {
/linux/arch/arm64/include/asm/
H A Del2_setup.h160 cbnz x0, .Lskip_trace_\@ // If TRBE is available at EL2