| /linux/drivers/gpu/drm/hisilicon/hibmc/dp/ |
| H A D | dp_link.c | 101 drm_dbg_dp(dp->dev, "dp aux write training pattern set failed\n"); in hibmc_dp_link_set_pattern()
131 drm_dbg_dp(dp->dev, "dp aux write training lane set failed\n"); in hibmc_dp_link_training_cr_pre()
186 drm_dbg_dp(dp->dev, "dp link training reduce to 1 lane\n"); in hibmc_dp_link_reduce_lane()
189 drm_err(dp->dev, "dp link training reduce lane failed, already reach minimum\n"); in hibmc_dp_link_reduce_lane()
222 drm_dbg_dp(dp->dev, "dp link training cr done\n"); in hibmc_dp_link_training_cr()
242 drm_dbg_dp(dp->dev, "Update link training failed\n"); in hibmc_dp_link_training_cr()
249 drm_err(dp->dev, "dp link training clock recovery 80 times failed\n"); in hibmc_dp_link_training_cr()
283 drm_dbg_dp(dp->dev, "dp link training eq done\n"); in hibmc_dp_link_training_channel_eq()
296 drm_dbg_dp(dp->dev, "Update link training failed\n"); in hibmc_dp_link_training_channel_eq()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | psp_v14_0.c | 58 /* memory training timeout define */
408 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", in psp_v14_0_memory_training_send_msg()
427 dev_dbg(adev->dev, "Memory training is not supported.\n"); in psp_v14_0_memory_training()
430 dev_err(adev->dev, "Memory training initialization failure.\n"); in psp_v14_0_memory_training()
435 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); in psp_v14_0_memory_training()
445 dev_dbg(adev->dev, "Short training depends on restore.\n"); in psp_v14_0_memory_training()
458 …dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); in psp_v14_0_memory_training()
464 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); in psp_v14_0_memory_training()
473 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); in psp_v14_0_memory_training()
477 * Long training will encroach a certain amount on the bottom of VRAM; in psp_v14_0_memory_training()
[all …]
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| H A D | psp_v13_0.c | 78 /* memory training timeout define */
549 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", in psp_v13_0_memory_training_send_msg()
568 dev_dbg(adev->dev, "Memory training is not supported.\n"); in psp_v13_0_memory_training()
571 dev_err(adev->dev, "Memory training initialization failure.\n"); in psp_v13_0_memory_training()
576 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); in psp_v13_0_memory_training()
586 dev_dbg(adev->dev, "Short training depends on restore.\n"); in psp_v13_0_memory_training()
599 …dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); in psp_v13_0_memory_training()
605 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); in psp_v13_0_memory_training()
614 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); in psp_v13_0_memory_training()
618 * Long training will encroach a certain amount on the bottom of VRAM; in psp_v13_0_memory_training()
[all …]
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| /linux/drivers/gpu/drm/bridge/analogix/ |
| H A D | analogix-i2c-dptx.h | 127 /* DP Training Pattern Set Register */
130 /* DP Lane 0 Link Training Control Register */
138 /* DP Link Training Control Register */
151 /* DP CEP Training Control Registers */
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| H A D | analogix_dp_core.c | 274 /* Set training pattern 1 */ in analogix_dp_link_start()
277 /* Set RX training pattern */ in analogix_dp_link_start()
402 /* set training pattern 2 for EQ */ in analogix_dp_process_clock_recovery()
411 dev_dbg(dp->dev, "Link Training Clock Recovery success\n"); in analogix_dp_process_clock_recovery()
490 dev_dbg(dp->dev, "Link Training success!\n"); in analogix_dp_process_equalizer_training()
614 dev_err(dp->dev, "eDP link training failed (%d)\n", retval); in analogix_dp_full_link_train()
639 /* source Set training pattern 1 */ in analogix_dp_fast_link_train()
652 * Useful for debugging issues with fast link training, disable for more in analogix_dp_fast_link_train()
832 dev_dbg(dp->dev, "fast link training %s\n", in analogix_dp_fast_link_train_detection()
866 /* Check whether panel supports fast training */ in analogix_dp_commit()
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| H A D | analogix-anx78xx.h | 219 /* DP TX Link Training Control Register */
222 /* PD 1.2 Lint Training 80bit Pattern Register */
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| /linux/Documentation/gpu/ |
| H A D | zynqmp.rst | 78 Link training symbol pattern TPS1 (/D10.2/)
81 Link training symbol pattern TPS2
84 Link training symbol pattern TPS3 (for HBR2)
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| /linux/arch/mips/cavium-octeon/executive/ |
| H A D | cvmx-spi.c | 123 /* Callback to perform SPI4 link training */ in cvmx_spi_start_interface()
168 /* Callback to perform SPI4 link training */ in cvmx_spi_restart_interface()
382 /* STX0 Training Control */ in cvmx_spi_calendar_setup_cb()
495 * Callback to perform link training
516 /* SRX0 & STX0 Inf0 Links are configured - begin training */ in cvmx_spi_training_cb()
537 /* Wait for the training sequence to complete */ in cvmx_spi_training_cb()
538 cvmx_dprintf("SPI%d: Waiting for training\n", interface); in cvmx_spi_training_cb()
543 * The HRM says we must wait for 34 + 16 * MAXDIST training sequences. in cvmx_spi_training_cb()
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| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_training_8b_10b.c | 27 * This file implements dp 8b/10b link training software policies and
195 * 6. Begin link training as usual in set_link_settings_and_perform_early_tps2_retimer_pre_lt_sequence()
331 …DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing iss… in perform_8b_10b_clock_recovery_sequence()
445 /* 2. perform link training (set link training done in dp_perform_8b_10b_link_training()
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| H A D | link_dp_training_dpia.h | 36 * Aborts link training upon detection of sink unplug.
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| H A D | dp.c | 209 OUTP_TRACE(outp, "training pattern %d", pattern); in nvkm_dp_train_pattern()
324 OUTP_DBG(outp, "training %dx%02x", ior->dp.nr, ior->dp.bw); in nvkm_dp_train_link()
354 OUTP_DBG(outp, "training LTTPR%d", lt.repeater); in nvkm_dp_train_link()
356 OUTP_DBG(outp, "training sink"); in nvkm_dp_train_link()
509 OUTP_DBG(outp, "training"); in nvkm_dp_train()
520 OUTP_ERR(outp, "training failed"); in nvkm_dp_train()
522 OUTP_DBG(outp, "training done"); in nvkm_dp_train()
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| /linux/drivers/pci/controller/ |
| H A D | pcie-rockchip-ep.c | 46 * @link_training: Work item to execute PCI link training.
486 /* Enable configuration and start link training */ in rockchip_pcie_ep_start()
510 /* Stop link training and disable configuration */ in rockchip_pcie_ep_stop()
542 /* Enable Gen1 training and wait for its completion */ in rockchip_pcie_ep_link_training()
620 dev_dbg(rockchip->dev, "PERST# de-asserted, starting link training\n"); in rockchip_pcie_ep_perst_deassert()
627 /* Enable link re-training */ in rockchip_pcie_ep_perst_deassert()
630 /* Start link training */ in rockchip_pcie_ep_perst_deassert()
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| /linux/Documentation/networking/device_drivers/atm/ |
| H A D | cxacru.rst | 77 - "training"
117 [4942253.654954] ATM dev 0: ADSL line: training
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_link_encoder.c | 296 /* Write Training Pattern */ in dce110_link_encoder_set_dp_phy_pattern_training_pattern()
300 /* Set HW Register Training Complete to false */ in dce110_link_encoder_set_dp_phy_pattern_training_pattern()
304 /* Disable PHY Bypass mode to output Training Pattern */ in dce110_link_encoder_set_dp_phy_pattern_training_pattern()
475 /* set link training complete */ in set_dp_phy_pattern_hbr2_compliance_cp2520_2()
527 /* set link training complete */ in dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2()
555 /* set link training complete */ in set_dp_phy_pattern_passthrough_mode()
583 /* set link training complete */ in dce60_set_dp_phy_pattern_passthrough_mode()
713 /* reset training pattern */ in link_encoder_disable()
717 /* reset training complete */ in link_encoder_disable()
1483 /* set DP PHY test and training patterns */
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| /linux/Documentation/accel/ |
| H A D | introduction.rst | 32 - Training data-center - Similar to Inference data-center cards, but typically
34 a method of scaling-up/out, i.e. connecting to other training cards inside
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| /linux/arch/arm/mach-mvebu/ |
| H A D | board-v7.c | 57 * bootloader, which executes its DDR3 training code. This code has
90 pr_warn("Too little memory to reserve for DDR training\n"); in mvebu_scan_mem()
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| /linux/include/linux/bcma/ |
| H A D | bcma_driver_pci.h | 117 #define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
118 #define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
119 #define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc.h | 1616 * for every link training. This is incompatible with DP LL compliance automation,
1659 * calls are not performed atomically (i.e. performing link training),
2381 /* Force DP link to customize a specific link training behavior by overriding to
2383 * display specific link training issues or apply some display specific
2384 * workaround in link training.
2388 * will apply this particular override in future link training. If NULL is
2391 * training settings.
2549 /* Obtain driver time stamp for last dp link training end. The time stamp is
2551 * @in_detection - true to get link training end time stamp of last link
2552 * training in detection sequence. false to get link training end time stamp
[all …]
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| /linux/drivers/gpu/drm/msm/dp/ |
| H A D | dp_ctrl.c | 1606 DRM_ERROR("link training #1 on phy %d failed. ret=%d\n", dp_phy, ret); in msm_dp_ctrl_link_train_1_2()
1609 drm_dbg_dp(ctrl->drm_dev, "link training #1 on phy %d successful\n", dp_phy); in msm_dp_ctrl_link_train_1_2()
1613 DRM_ERROR("link training #2 on phy %d failed. ret=%d\n", dp_phy, ret); in msm_dp_ctrl_link_train_1_2()
1616 drm_dbg_dp(ctrl->drm_dev, "link training #2 on phy %d successful\n", dp_phy); in msm_dp_ctrl_link_train_1_2()
1662 DRM_ERROR("link training of LTTPR(s) failed. ret=%d\n", ret); in msm_dp_ctrl_link_train()
1668 DRM_ERROR("link training on sink failed. ret=%d\n", ret); in msm_dp_ctrl_link_train()
1691 * a link training pattern, we have to first do soft reset. in msm_dp_ctrl_setup_main_link()
2321 /* training completed successfully */ in msm_dp_ctrl_on_link()
2366 /* stop link training before start re training */ in msm_dp_ctrl_on_link()
2383 * stop link training at on_stream in msm_dp_ctrl_on_link()
[all …]
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| H A D | dp_link.c | 531 * msm_dp_link_parse_link_training_params() - parses link training parameters from
741 * msm_dp_link_process_link_training_request() - processes new training requests
744 * This function will handle new link training requests that are initiated by
748 * The function will return 0 if a link training request has been processed,
951 * recovery done on all lanes, and trigger link training if there is a
1031 * the start of a new link training request or sink status update.
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| /linux/drivers/gpu/drm/xlnx/ |
| H A D | zynqmp_dp.c | 291 * @TEST_TPS1: Link training symbol pattern TPS1 (/D10.2/)
292 * @TEST_TPS2: Link training symbol pattern TPS2
293 * @TEST_TPS3: Link training symbol pattern TPS3 (for HBR2)
372 * @train_set: set of training data
614 * DisplayPort Link Training
692 * @link_status: link status from sink which contains requested training values
716 * zynqmp_dp_update_vs_emph - Update the training values
718 * @train_set: A set of training values
720 * Update the training values based on the request from sink. The mapped values
969 dev_err(dp->dev, "failed to disable training pattern\n"); in zynqmp_dp_train()
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| /linux/drivers/gpu/drm/bridge/ |
| H A D | tc358767.c | 242 /* Link Training */
565 * No training pattern, skew lane 1 data by two LSCLK cycles with in tc_srcctrl()
1076 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n"); in tc_wait_link_training()
1190 /* Setup Link & DPRx Config for Training */ in tc_main_link_enable()
1220 /* Set DPCD 0x102 for Training Pattern 1 */ in tc_main_link_enable()
1243 /* Enable DP0 to start Link Training */ in tc_main_link_enable()
1257 dev_err(tc->dev, "Link training phase 1 failed: %s\n", in tc_main_link_enable()
1264 /* Set DPCD 0x102 for Training Pattern 2 */ in tc_main_link_enable()
1286 dev_err(tc->dev, "Link training phase 2 failed: %s\n", in tc_main_link_enable()
1293 * clear the training pattern bit in DP0_SRCCTRL. Testing shows in tc_main_link_enable()
[all …]
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| /linux/Documentation/scsi/ |
| H A D | aic79xx.rst | 31 Ultra320 SCSI ASIC with Retained Training
35 Ultra320 SCSI ASIC with Retained Training
171 interveining training.
207 - Retained Training Information (Rev B. ASIC only)
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| /linux/drivers/usb/host/ |
| H A D | xhci-port.h | 76 * also resets the link, forcing the device through the link training sequence.
177 * to complete link training. usually link trainig completes much faster
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| /linux/tools/thermal/tmon/ |
| H A D | README | 30 that can be used for thermal relationship training.
|