xref: /linux/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml (revision 3fd6c59042dbba50391e30862beac979491145fe) 
1# SPDX-License-Identifier: GPL-2.0+
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/nxp,tja11xx.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP TJA11xx PHY
8
9maintainers:
10  - Andrew Lunn <andrew@lunn.ch>
11  - Florian Fainelli <f.fainelli@gmail.com>
12  - Heiner Kallweit <hkallweit1@gmail.com>
13
14description:
15  Bindings for NXP TJA11xx automotive PHYs
16
17properties:
18  compatible:
19    enum:
20      - ethernet-phy-id0180.dc40
21      - ethernet-phy-id0180.dc41
22      - ethernet-phy-id0180.dc48
23      - ethernet-phy-id0180.dd00
24      - ethernet-phy-id0180.dd01
25      - ethernet-phy-id0180.dd02
26      - ethernet-phy-id0180.dc80
27      - ethernet-phy-id0180.dc82
28      - ethernet-phy-id001b.b010
29      - ethernet-phy-id001b.b013
30      - ethernet-phy-id001b.b030
31      - ethernet-phy-id001b.b031
32
33allOf:
34  - $ref: ethernet-phy.yaml#
35  - if:
36      properties:
37        compatible:
38          contains:
39            enum:
40              - ethernet-phy-id0180.dc40
41              - ethernet-phy-id0180.dc41
42              - ethernet-phy-id0180.dc48
43              - ethernet-phy-id0180.dd00
44              - ethernet-phy-id0180.dd01
45              - ethernet-phy-id0180.dd02
46
47    then:
48      properties:
49        nxp,rmii-refclk-in:
50          type: boolean
51          description: |
52            The REF_CLK is provided for both transmitted and received data
53            in RMII mode. This clock signal is provided by the PHY and is
54            typically derived from an external 25MHz crystal. Alternatively,
55            a 50MHz clock signal generated by an external oscillator can be
56            connected to pin REF_CLK. A third option is to connect a 25MHz
57            clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
58            as input or output according to the actual circuit connection.
59            If present, indicates that the REF_CLK will be configured as
60            interface reference clock input when RMII mode enabled.
61            If not present, the REF_CLK will be configured as interface
62            reference clock output when RMII mode enabled.
63            Only supported on TJA1100 and TJA1101.
64
65  - if:
66      properties:
67        compatible:
68          contains:
69            enum:
70              - ethernet-phy-id001b.b010
71              - ethernet-phy-id001b.b013
72              - ethernet-phy-id001b.b030
73              - ethernet-phy-id001b.b031
74
75    then:
76      properties:
77        nxp,rmii-refclk-out:
78          type: boolean
79          description: Enable 50MHz RMII reference clock output on REF_CLK pin.
80
81patternProperties:
82  "^ethernet-phy@[0-9a-f]+$":
83    type: object
84    additionalProperties: false
85    description: |
86      Some packages have multiple PHYs. Secondary PHY should be defines as
87      subnode of the first (parent) PHY.
88
89    properties:
90      reg:
91        minimum: 0
92        maximum: 31
93        description:
94          The ID number for the child PHY. Should be +1 of parent PHY.
95
96    required:
97      - reg
98
99unevaluatedProperties: false
100
101examples:
102  - |
103    mdio {
104        #address-cells = <1>;
105        #size-cells = <0>;
106
107        tja1101_phy0: ethernet-phy@4 {
108            compatible = "ethernet-phy-id0180.dc40";
109            reg = <0x4>;
110            nxp,rmii-refclk-in;
111        };
112    };
113  - |
114    mdio {
115        #address-cells = <1>;
116        #size-cells = <0>;
117
118        tja1102_phy0: ethernet-phy@4 {
119            reg = <0x4>;
120            #address-cells = <1>;
121            #size-cells = <0>;
122
123            tja1102_phy1: ethernet-phy@5 {
124                reg = <0x5>;
125            };
126        };
127    };
128