| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | sdhci-sprd.txt | 1 * Spreadtrum SDHCI controller (sdhci-sprd)
3 The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
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| H A D | exynos-dw-mshc.txt | 2 Storage Host Controller
4 The Synopsys designware mobile storage host controller is used to interface
6 differences between the core Synopsys dw mshc controller properties described
7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
8 extensions to the Synopsys Designware Mobile Storage Host Controller.
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
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| H A D | sdhci-am654.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI AM654 MMC Controller
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
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| H A D | samsung,exynos-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 Storage Host Controller
12 - Jaehoon Chung <jh80.chung@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - enum:
19 - axis,artpec8-dw-mshc
20 - samsung,exynos4210-dw-mshc
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| H A D | cdns,sdhci.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - microchip,pic64gx-sd4hc
19 - mobileye,eyeq-sd4hc
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | nvidia,tegra124-car.txt | 1 NVIDIA Tegra124 and Tegra132 Clock And Reset Controller
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
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| /freebsd/sys/contrib/device-tree/Bindings/ata/ |
| H A D | ahci-ceva.txt | 1 Binding for CEVA AHCI SATA Controller
4 - reg: Physical base address and size of the controller's register area.
5 - compatible: Compatibility string. Must be 'ceva,ahci-1v84'.
6 - clocks: Input clock specifier. Refer to common clock bindings.
7 - interrupts: Interrupt specifier. Refer to interrupt binding.
8 - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
9 - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1.
11 ceva,pN-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
16 - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
17 - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1.
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| H A D | ceva,ahci-1v84.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ceva AHCI SATA Controller
10 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
13 The Ceva SATA controller mostly conforms to the AHCI interface with some
14 special extensions to add functionality, is a high-performance dual-port
15 SATA host controller with an AHCI compliant command layer which supports
21 const: ceva,ahci-1v84
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| /freebsd/sys/contrib/device-tree/Bindings/media/xilinx/ |
| H A D | xlnx,v-tc.txt | 1 Xilinx Video Timing Controller (VTC)
2 ------------------------------------
4 The Video Timing Controller is a general purpose video timing generator and
9 - compatible: Must be "xlnx,v-tc-6.1".
11 - reg: Physical base address and length of the registers set for the device.
13 - clocks: Must contain a clock specifier for the VTC core and timing
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
28 compatible = "xlnx,v-tc-6.1";
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| H A D | xlnx,v-tpg.txt | 2 -----------------------------------------
6 - compatible: Must contain at least one of
8 "xlnx,v-tpg-5.0" (TPG version 5.0)
9 "xlnx,v-tpg-6.0" (TPG version 6.0)
11 TPG versions backward-compatible with previous versions should list all
14 - reg: Physical base address and length of the registers set for the device.
16 - clocks: Reference to the video core clock.
18 - xlnx,video-format, xlnx,video-width: Video format and width, as defined in
21 - port: Video port, using the DT bindings defined in ../video-interfaces.txt.
26 - xlnx,vtc: A phandle referencing the Video Timing Controller that generates
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| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | intel,ixp4xx-expansion-bus-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel IXP4xx Expansion Bus Controller
10 The IXP4xx expansion bus controller handles access to devices on the
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
15 - Linus Walleij <linus.walleij@linaro.org>
19 pattern: '^bus@[0-9a-f]+$'
23 - enum:
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| /freebsd/sys/contrib/device-tree/Bindings/display/exynos/ |
| H A D | exynos7-decon.txt | 1 Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON)
3 DECON (Display and Enhancement Controller) is the Display Controller for the
8 - compatible: value should be "samsung,exynos7-decon";
10 - reg: physical base address and length of the DECON registers set.
12 - interrupts: should contain a list of all DECON IP block interrupts in the
14 format depends on the interrupt controller used.
16 - interrupt-names: should contain the interrupt names: "fifo", "vsync",
20 - pinctrl-0: pin control group to be used for this controller.
22 - pinctrl-names: must contain a "default" entry.
24 - clocks: must include clock specifiers corresponding to entries in the
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| H A D | samsung-fimd.txt | 1 Device-Tree bindings for Samsung SoC display controller (FIMD)
3 FIMD (Fully Interactive Mobile Display) is the Display Controller for the
8 - compatible: value should be one of the following
9 "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
10 "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
11 "samsung,s5pv210-fimd"; /* for S5PV210 SoC */
12 "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
13 "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
14 "samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
15 "samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
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| /freebsd/sys/contrib/device-tree/Bindings/display/panel/ |
| H A D | panel-mipi-dbi-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Noralf Trønnes <noralf@tronnes.org>
13 This binding is for display panels using a MIPI DBI compatible controller
23 - Power:
24 - Vdd: Power supply for display module
25 Called power-supply in this binding.
26 - Vddi: Logic level supply for interface signals
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| H A D | panel-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
24 width-mm:
29 height-mm:
43 non-descriptive information. For instance an LCD panel in a system that
54 flip-horizontal:
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| H A D | olimex,lcd-olinuxino.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/olimex,lcd-olinuxino.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Olimex Ltd. LCD-OLinuXino bridge panel.
10 - Stefan Mavrodiev <stefan@olimex.com>
13 This device can be used as bridge between a host controller and LCD panels.
15 - LCD-OLinuXino-4.3TS
16 - LCD-OLinuXino-5
17 - LCD-OLinuXino-7
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/fsl/ |
| H A D | fsl,imx-weim.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
16 wireless and mobile applications that use low-power technology. The actual
21 pattern: "^memory-controller@[0-9a-f]+$"
25 - enum:
26 - fsl,imx1-weim
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| /freebsd/sys/contrib/edk2/Include/Protocol/ |
| H A D | IdeControllerInit.h | 2 This file declares EFI IDE Controller Init Protocol
4 The EFI_IDE_CONTROLLER_INIT_PROTOCOL provides the chipset-specific information
6 IDE devices behind the controller are to be enumerated by a driver entity.
9 controller in a system. It is installed on the handle that corresponds to the
10 IDE controller. A driver entity that wishes to manage an IDE bus and possibly
12 instance that is associated with the controller to be managed.
14 A device handle for an IDE controller must contain an EFI_DEVICE_PATH_PROTOCOL.
16 Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
17 SPDX-License-Identifier: BSD-2-Clause-Patent
44 /// The phase of the IDE Controller enumeration.
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| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | sitronix,st7567.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sitronix ST7567 Display Controller
10 - Javier Martinez Canillas <javierm@redhat.com>
13 Sitronix ST7567 is a driver and controller for monochrome
17 - $ref: panel/panel-common.yaml#
26 width-mm: true
27 height-mm: true
28 panel-timing: true
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| H A D | sitronix,st7571.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sitronix ST7571 Display Controller
10 - Marcus Folkesson <marcus.folkesson@gmail.com>
13 Sitronix ST7571 is a driver and controller for 4-level gray
17 - $ref: panel/panel-common.yaml#
29 Display supports 4-level grayscale.
31 reset-gpios: true
32 width-mm: true
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | nvidia,tegra124-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
16 two memory channels. The Tegra124 Memory Controller handles memory requests
22 const: nvidia,tegra124-mc
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| H A D | nvidia,tegra30-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra30 SoC Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 Tegra30 Memory Controller architecturally consists of the following parts:
33 The Tegra30 Memory Controller handles memory requests from internal clients
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| H A D | nvidia,tegra30-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra30 SoC External Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
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| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | vf610-nfc.txt | 1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
7 - compatible: Should be set to "fsl,vf610-nfc".
8 - reg: address range of the NFC.
9 - interrupts: interrupt of the NFC.
10 - #address-cells: shall be set to 1. Encode the nand CS.
11 - #size-cells : shall be set to 0.
12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-sprd-adi.txt | 1 Spreadtrum ADI controller
3 ADI is the abbreviation of Anolog-Digital interface, which is used to access
4 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
5 framework for its hardware implementation is alike to SPI bus and its timing
6 is compatile to SPI timing.
8 ADI controller has 50 channels including 2 software read/write channels and
16 Thus we introduce one property named "sprd,hw-channels" to configure hardware
21 Since we have multi-subsystems will use unique ADI to access analog chip, when
25 ADI registers will make ADI controller registers chaos to lead incorrect results.
28 The new version ADI controller supplies multiple master channels for different
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