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/linux/Documentation/devicetree/bindings/timer/
H A Dcdns,ttc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/cdns,ttc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence TTC - Triple Timer Counter
10 - Michal Simek <michal.simek@amd.com>
22 A list of 3 interrupts; one per timer channel.
27 power-domains:
30 timer-width:
33 Bit width of the timer, necessary if not 16.
[all …]
H A Dnxp,tpm-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP Low Power Timer/Pulse Width Modulation Module (TPM)
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The Timer/PWM Module (TPM) supports input capture, output compare,
18 the counter bus for the others, provided bit width is the same.
23 - const: fsl,imx7ulp-tpm
24 - items:
[all …]
/linux/drivers/clocksource/
H A Dtimer-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Inspired by time-efm32.c from Uwe Kleine-Koenig
23 #include "timer-of.h"
54 * stm32_timer_of_bits_set - set accessor helper
58 * Accessor helper to set the number of bits in the timer-of private
64 struct stm32_timer_private *pd = to->private_data; in stm32_timer_of_bits_set()
66 pd->bits = bits; in stm32_timer_of_bits_set()
70 * stm32_timer_of_bits_get - get accessor helper
73 * Accessor helper to get the number of bits in the timer-of private
80 struct stm32_timer_private *pd = to->private_data; in stm32_timer_of_bits_get()
[all …]
/linux/drivers/pwm/
H A Dpwm-dwc-core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2020 Intel Corporation
22 #include "pwm-dwc.h"
48 * Calculate width of low and high period in terms of input clock in __dwc_pwm_configure_timer()
52 tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); in __dwc_pwm_configure_timer()
54 return -ERANGE; in __dwc_pwm_configure_timer()
55 low = tmp - 1; in __dwc_pwm_configure_timer()
57 tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, in __dwc_pwm_configure_timer()
58 dwc->clk_ns); in __dwc_pwm_configure_timer()
60 return -ERANGE; in __dwc_pwm_configure_timer()
[all …]
/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
21 * Since this is a non-ratified draft specification, the kernel does not
[all …]
/linux/arch/m68k/include/asm/
H A DMC68328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
76 #define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
[all …]
H A DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
[all …]
H A DMC68VZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
55 * 0xFFFFF1xx -- Chip-Select logic
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91-sam9_l9260.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-sam9_l9260.dts - Device Tree file for Olimex SAM9-L9260 board
7 /dts-v1/;
11 model = "Olimex sam9-l9260";
12 compatible = "olimex,sam9-l9260", "atmel,at91sam9260", "atmel,at91sam9";
15 stdout-path = "serial0:115200n8";
24 clock-frequency = <32768>;
28 clock-frequency = <18432000>;
34 tcb0: timer@fffa0000 {
35 timer@0 {
[all …]
H A Dat91sam9260ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
17 stdout-path = &dbgu;
26 clock-frequency = <32768>;
30 clock-frequency = <18432000>;
36 tcb0: timer@fffa0000 {
37 timer@0 {
38 compatible = "atmel,tcb-timer";
42 timer@2 {
[all …]
H A Dat91sam9m10g45ek.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
8 /dts-v1/;
10 #include <dt-bindings/pwm/pwm.h>
13 model = "Atmel AT91SAM9M10G45-EK";
18 stdout-path = "serial0:115200n8";
27 clock-frequency = <32768>;
31 clock-frequency = <12000000>;
41 tcb0: timer@fff7c000 {
42 timer@0 {
[all …]
H A Dsama5d3xcm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module
14 stdout-path = "serial0:115200n8";
23 clock-frequency = <32768>;
27 clock-frequency = <12000000>;
34 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
37 tcb0: timer@f0010000 {
38 timer@0 {
39 compatible = "atmel,tcb-timer";
43 timer@1 {
[all …]
H A Dpm9g45.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * pm9g45.dts - Device Tree file for Ronetix pm9g45 board
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 /dts-v1/;
24 clock-frequency = <32768>;
28 clock-frequency = <12000000>;
40 pinctrl_nand_rb: nand-rb-0 {
47 pinctrl_board_mmc: mmc0-board {
54 tcb0: timer@fff7c000 {
55 timer@0 {
[all …]
H A Dat91-qil_a9260.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91-qil_a9260.dts - Device Tree file for Calao QIL A9260 board
5 * Copyright (C) 2011-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 /dts-v1/;
11 compatible = "calao,qil-a9260", "atmel,at91sam9260", "atmel,at91sam9";
23 clock-frequency = <32768>;
27 clock-frequency = <12000000>;
33 tcb0: timer@fffa0000 {
34 timer@0 {
35 compatible = "atmel,tcb-timer";
[all …]
H A Dat91-cosino.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-cosino.dtsi - Device Tree file for Cosino core module
5 * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it>
29 clock-frequency = <32768>;
33 clock-frequency = <12000000>;
39 atmel,adc-ts-wires = <4>;
40 atmel,adc-ts-pressure-threshold = <10000>;
49 pinctrl-0 = <&pinctrl_ebi_addr_nand
51 pinctrl-names = "default";
54 nand-controller {
[all …]
H A Danimeo_ip.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 /dts-v1/;
13 compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9";
26 stdout-path = &usart2;
35 clock-frequency = <32768>;
39 clock-frequency = <18432000>;
45 tcb0: timer@fffa0000 {
46 timer@0 {
[all …]
H A Dat91-sama5d3_xplained.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
14 compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5";
17 stdout-path = "serial0:115200n8";
26 clock-frequency = <32768>;
30 clock-frequency = <12000000>;
37 …pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd…
38 vmmc-supply = <&vcc_mmc0_reg>;
[all …]
H A Dat91-sama5d4ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
8 /dts-v1/;
12 model = "Atmel SAMA5D4-EK";
16 stdout-path = "serial0:115200n8";
25 clock-frequency = <32768>;
29 clock-frequency = <12000000>;
36 pinctrl-names = "default";
37 pinctrl-0 = <
45 /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
[all …]
/linux/tools/testing/selftests/kvm/arm64/
H A Darch_timer_edge_cases.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch_timer_edge_cases.c - Tests the aarch64 timer IRQ functionality.
5 * The test validates some edge cases related to the arch-timer:
6 * - timers above the max TVAL value.
7 * - timer
54 enum arch_timer timer; global() member
140 set_counter(enum arch_timer timer,u64 counter) set_counter() argument
148 enum arch_timer timer; guest_irq_handler() local
181 set_cval_irq(enum arch_timer timer,u64 cval_cycles,u32 ctl) set_cval_irq() argument
190 set_tval_irq(enum arch_timer timer,u64 tval_cycles,u32 ctl) set_tval_irq() argument
199 set_xval_irq(enum arch_timer timer,u64 xval,u32 ctl,enum timer_view tv) set_xval_irq() argument
294 sleep_poll(enum arch_timer timer,u64 usec) sleep_poll() argument
299 sleep_sched_poll(enum arch_timer timer,u64 usec) sleep_sched_poll() argument
304 sleep_migrate(enum arch_timer timer,u64 usec) sleep_migrate() argument
309 sleep_in_userspace(enum arch_timer timer,u64 usec) sleep_in_userspace() argument
318 reset_timer_state(enum arch_timer timer,u64 cnt) reset_timer_state() argument
324 test_timer_xval(enum arch_timer timer,u64 xval,enum timer_view tv,irq_wait_method_t wm,bool reset_state,u64 reset_cnt) test_timer_xval() argument
351 test_timer_cval(enum arch_timer timer,u64 cval,irq_wait_method_t wm,bool reset_state,u64 reset_cnt) test_timer_cval() argument
358 test_timer_tval(enum arch_timer timer,s32 tval,irq_wait_method_t wm,bool reset_state,u64 reset_cnt) test_timer_tval() argument
366 test_xval_check_no_irq(enum arch_timer timer,u64 xval,u64 usec,enum timer_view timer_view,sleep_method_t guest_sleep) test_xval_check_no_irq() argument
382 test_cval_no_irq(enum arch_timer timer,u64 cval,u64 usec,sleep_method_t wm) test_cval_no_irq() argument
388 test_tval_no_irq(enum arch_timer timer,s32 tval,u64 usec,sleep_method_t wm) test_tval_no_irq() argument
396 test_timer_control_mask_then_unmask(enum arch_timer timer) test_timer_control_mask_then_unmask() argument
412 test_timer_control_masks(enum arch_timer timer) test_timer_control_masks() argument
427 test_fire_a_timer_multiple_times(enum arch_timer timer,irq_wait_method_t wm,int num) test_fire_a_timer_multiple_times() argument
452 test_timers_fired_multiple_times(enum arch_timer timer) test_timers_fired_multiple_times() argument
465 test_reprogramming_timer(enum arch_timer timer,irq_wait_method_t wm,s32 delta_1_ms,s32 delta_2_ms) test_reprogramming_timer() argument
488 test_reprogram_timers(enum arch_timer timer) test_reprogram_timers() argument
505 test_basic_functionality(enum arch_timer timer) test_basic_functionality() argument
523 timers_sanity_checks(enum arch_timer timer,bool use_sched) timers_sanity_checks() argument
583 test_timers_sanity_checks(enum arch_timer timer) test_timers_sanity_checks() argument
590 test_set_cnt_after_tval_max(enum arch_timer timer,irq_wait_method_t wm) test_set_cnt_after_tval_max() argument
609 test_timers_above_tval_max(enum arch_timer timer) test_timers_above_tval_max() argument
641 test_set_cnt_after_xval(enum arch_timer timer,u64 cnt_1,u64 xval,u64 cnt_2,irq_wait_method_t wm,enum timer_view tv) test_set_cnt_after_xval() argument
664 test_set_cnt_after_xval_no_irq(enum arch_timer timer,u64 cnt_1,u64 xval,u64 cnt_2,sleep_method_t guest_sleep,enum timer_view tv) test_set_cnt_after_xval_no_irq() argument
687 test_set_cnt_after_tval(enum arch_timer timer,u64 cnt_1,s32 tval,u64 cnt_2,irq_wait_method_t wm) test_set_cnt_after_tval() argument
694 test_set_cnt_after_cval(enum arch_timer timer,u64 cnt_1,u64 cval,u64 cnt_2,irq_wait_method_t wm) test_set_cnt_after_cval() argument
701 test_set_cnt_after_tval_no_irq(enum arch_timer timer,u64 cnt_1,s32 tval,u64 cnt_2,sleep_method_t wm) test_set_cnt_after_tval_no_irq() argument
709 test_set_cnt_after_cval_no_irq(enum arch_timer timer,u64 cnt_1,u64 cval,u64 cnt_2,sleep_method_t wm) test_set_cnt_after_cval_no_irq() argument
718 test_move_counters_ahead_of_timers(enum arch_timer timer) test_move_counters_ahead_of_timers() argument
741 test_move_counters_behind_timers(enum arch_timer timer) test_move_counters_behind_timers() argument
754 test_timers_in_the_past(enum arch_timer timer) test_timers_in_the_past() argument
790 test_long_timer_delays(enum arch_timer timer) test_long_timer_delays() argument
804 guest_run_iteration(enum arch_timer timer) guest_run_iteration() argument
822 guest_code(enum arch_timer timer) guest_code() argument
865 kvm_set_cntxct(struct kvm_vcpu * vcpu,u64 cnt,enum arch_timer timer) kvm_set_cntxct() argument
877 enum arch_timer timer = uc->args[3]; handle_sync() local
936 test_vm_create(struct kvm_vm ** vm,struct kvm_vcpu ** vcpu,enum arch_timer timer) test_vm_create() argument
1022 int width = ilog2(MIN_ROLLOVER_SECS * freq); set_counter_defaults() local
[all...]
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/linux/drivers/media/i2c/cx25840/
H A Dcx25840-ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/drv-intf/cx25840.h>
14 #include <media/rc-core.h>
16 #include "cx25840-core.h"
117 return state ? state->ir_state : NULL; in to_ir_state()
135 d--; in count_to_clock_divider()
193 * FIFO register pulse width count computations
199 * the pulse width counter as read from the FIFO. The two lsb's are in clock_divider_to_resolution()
212 * The 2 lsb's of the pulse width timer count are not readable, hence in pulse_width_count_to_ns()
231 * The 2 lsb's of the pulse width timer count are not accessible, hence
[all …]
/linux/arch/mips/ath25/
H A Dar5312_regs.h64 #define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
65 #define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
67 /* Reset/Timer Block Address Map */
68 #define AR5312_TIMER 0x0000 /* countdown timer */
69 #define AR5312_RELOAD 0x0004 /* timer reload value */
71 #define AR5312_WDT_TIMER 0x000c /* watchdog timer */
177 * ARM Flash Controller -- 3 flash banks with either x8 or x16 devices
206 #define AR5312_FLASHCTL_MW 0x30000000 /* Mem width */
207 #define AR5312_FLASHCTL_MW8 0x00000000 /* Mem width x8 */
208 #define AR5312_FLASHCTL_MW16 0x10000000 /* Mem width x16 */
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/synaptics/
H A Dberlin2.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,berlin-smp";
34 next-level-cache = <&l2>;
38 clock-latency = <100000>;
[all …]
/linux/include/video/
H A Dsticore.h1 /* SPDX-License-Identifier: GPL-2.0 */
43 #define sti_onscreen_x(sti) (sti->glob_cfg->onscreen_x)
44 #define sti_onscreen_y(sti) (sti->glob_cfg->onscreen_y)
47 #define sti_font_x(sti) (PTR_STI(sti->font)->width)
48 #define sti_font_y(sti) (PTR_STI(sti->font)->height)
86 s16 onscreen_x; /* screen width in pixels */
88 s16 offscreen_x; /* offset width in pixels */
90 s16 total_x; /* frame buffer width in pixels */
105 u32 nontext : 1; /* turn on non-text display planes? */
107 u32 cmap_blk : 1; /* non-text planes cmap black? */
[all …]

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