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/linux/arch/powerpc/boot/
H A Dpq2.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include "fsl-soc.h"
21 3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, -1,
22 6, 5, 13, 2, 14, 4, 15, 9, 0, 11, 8, 10, 16, 12, 7, -1
25 /* Get various clocks from crystal frequency.
26 * Returns zero on failure and non-zero on success.
29 u32 *timebase, u32 *brgfreq) in pq2_get_clocks() argument
55 if (timebase) in pq2_get_clocks()
56 *timebase = busclk / 4; in pq2_get_clocks()
75 void pq2_set_clocks(u32 sysfreq, u32 corefreq, u32 timebase, u32 brgfreq) in pq2_set_clocks() argument
[all …]
H A Dtreeboot-akebono.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Copyright 2002-2005 MontaVista Software Inc.
77 /* Fixup the SD timeout frequency */ in ibm_akebono_fixups()
80 /* Disable SD high-speed mode (which seems to be broken) */ in ibm_akebono_fixups()
88 setprop(emac, "local-mac-address", in ibm_akebono_fixups()
98 const u32 *timebase; in platform_init() local
102 userdata[USERDATA_LEN - 1] = '\0'; in platform_init()
104 for (i = 0; i < userdata_len - 15; i++) { in platform_init()
105 if (strncmp(&userdata[i], "local-mac-addr=", 15) == 0) { in platform_init()
106 if (i > 0 && userdata[i - 1] != ' ') { in platform_init()
[all …]
H A Dsimpleboot.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * The simple platform -- for booting when firmware doesn't supply a device
28 const u32 *na, *ns, *reg, *timebase; in platform_init() local
36 /* Find the #address-cells and #size-cells properties */ in platform_init()
40 na = fdt_getprop(_dtb_start, node, "#address-cells", &size); in platform_init()
42 fatal("Cannot find #address-cells property"); in platform_init()
43 ns = fdt_getprop(_dtb_start, node, "#size-cells", &size); in platform_init()
45 fatal("Cannot find #size-cells property"); in platform_init()
48 node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type", in platform_init()
68 /* finally, setup the timebase */ in platform_init()
[all …]
H A Dtreeboot-currituck.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Copyright 2002-2005 MontaVista Software Inc.
67 if (getprop(devp, "dma-ranges", dma_ranges, sizeof(dma_ranges)) < 0) { in ibm_currituck_fixups()
68 printf("%s: Failed to get dma-ranges\r\n", __func__); in ibm_currituck_fixups()
75 setprop(devp, "dma-ranges", dma_ranges, sizeof(dma_ranges)); in ibm_currituck_fixups()
85 const u32 *timebase; in platform_init() local
92 avail_ram = end_of_ram - (unsigned long)_end; in platform_init()
103 node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type", in platform_init()
107 timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size); in platform_init()
108 if (timebase && (size == 4)) in platform_init()
[all …]
H A Ddevtree.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * devtree.c - convenience functions for device tree manipulation
25 if (getprop(root, "#address-cells", &naddr, sizeof(naddr)) < 0) in dt_fixup_memory()
30 fatal("Can't cope with #address-cells == %d in /\n\r", naddr); in dt_fixup_memory()
32 if (getprop(root, "#size-cells", &nsize, sizeof(nsize)) < 0) in dt_fixup_memory()
37 fatal("Can't cope with #size-cells == %d in /\n\r", nsize); in dt_fixup_memory()
53 printf("Memory <- <0x%x", be32_to_cpu(memreg[0])); in dt_fixup_memory()
67 printf("CPU clock-frequency <- 0x%x (%dMHz)\n\r", cpu, MHZ(cpu)); in dt_fixup_cpu_clocks()
68 printf("CPU timebase-frequency <- 0x%x (%dMHz)\n\r", tb, MHZ(tb)); in dt_fixup_cpu_clocks()
70 printf("CPU bus-frequency <- 0x%x (%dMHz)\n\r", bus, MHZ(bus)); in dt_fixup_cpu_clocks()
[all …]
/linux/Documentation/devicetree/bindings/watchdog/
H A Dxlnx,xps-timebase-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Srinivas Neeli <srinivas.neeli@amd.com>
14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
22 - $ref: watchdog.yaml#
27 - xlnx,xps-timebase-wdt-1.01.a
[all …]
/linux/arch/powerpc/boot/dts/
H A Diss4xx-mpic.dts15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <100000000>; // 100Mhz :-)
39 timebase-frequency = <100000000>;
[all …]
H A Dps3.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
14 #size-cells = <2>;
15 #address-cells = <2>;
33 * dtc expects a clock-frequency and timebase-frequency entries, so
38 * threads is with an ibm,ppc-interrupt-server#s entry. We'll put one
43 #size-cells = <0>;
44 #address-cells = <1>;
49 ibm,ppc-interrupt-server#s = <0x0 0x1>;
50 clock-frequency = <0>;
[all …]
H A Dcurrituck.dts11 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
[all …]
H A Dgamecube.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2007-2009 The GameCube Linux Team
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 bootargs = "root=/dev/gcnsda2 rootwait udbg-immortal";
28 #address-cells = <1>;
29 #size-cells = <0>;
34 clock-frequency = <486000000>; /* 486MHz */
35 bus-frequency = <162000000>; /* 162MHz core-to-bus 3x */
[all …]
H A Diss4xx.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
20 model = "ibm,iss-4xx";
21 compatible = "ibm,iss-4xx";
22 dcr-parent = <&{/cpus/cpu@0}>;
29 #address-cells = <1>;
30 #size-cells = <0>;
36 clock-frequency = <100000000>; // 100Mhz :-)
37 timebase-frequency = <100000000>;
[all …]
H A Dstorcenter.dts14 /dts-v1/;
19 #address-cells = <1>;
20 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 clock-frequency = <200000000>;
36 timebase-frequency = <25000000>;
37 bus-frequency = <0>; /* from bootwrapper */
38 i-cache-line-size = <32>;
39 d-cache-line-size = <32>;
[all …]
H A Dmedia5200.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
12 &gpt0 { fsl,has-wdt; };
24 stdout-path = &console;
29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
30 bus-frequency = <132000000>; // 132 MHz
31 clock-frequency = <396000000>; // 396 MHz
40 bus-frequency = <132000000>;// 132 MHz
64 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
68 phy-handle = <&phy0>;
72 phy0: ethernet-phy@0 {
[all …]
/linux/arch/powerpc/platforms/8xx/
H A Dm8xx_setup.c1 // SPDX-License-Identifier: GPL-2.0
45 /* The cpu node should have timebase and clock frequency properties */ in get_freq()
61 /* The decrementer counts at the system (internal) clock frequency divided by
71 out_be32(&mpc8xx_immr->im_clkrstk.cark_sccrk, ~KAPWR_KEY); in mpc8xx_calibrate_decr()
72 out_be32(&mpc8xx_immr->im_clkrstk.cark_sccrk, KAPWR_KEY); in mpc8xx_calibrate_decr()
75 setbits32(&mpc8xx_immr->im_clkrst.car_sccr, 0x02000000); in mpc8xx_calibrate_decr()
77 /* Processor frequency is MHz. in mpc8xx_calibrate_decr()
80 if (!get_freq("clock-frequency", &ppc_proc_freq)) in mpc8xx_calibrate_decr()
81 printk(KERN_ERR "WARNING: Estimating processor frequency " in mpc8xx_calibrate_decr()
85 printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq); in mpc8xx_calibrate_decr()
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8641si-pre.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
8 /dts-v1/;
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&mpic>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
[all …]
/linux/drivers/pwm/
H A Dpwm-img.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2015, Imagination Technologies
7 * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
43 * PWM period is specified with a timebase register,
45 * specified in step periods, in the [0, $timebase] range.
46 * In other words, the timebase imposes the duty cycle
47 * resolution. Therefore, let's constraint the timebase to
49 * Imposing a minimum timebase, will impose a maximum PWM frequency.
81 writel(val, imgchip->base + reg); in img_pwm_writel()
86 return readl(imgchip->base + reg); in img_pwm_readl()
[all …]
/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
[all …]
/linux/arch/riscv/kernel/
H A Dtime.c1 // SPDX-License-Identifier: GPL-2.0-only
29 if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop)) in time_init()
30 panic("RISC-V system with no 'timebase-frequency' in DTS\n"); in time_init()
38 panic("RISC-V ACPI system with no RHCT table\n"); in time_init()
40 riscv_timebase = rhct->time_base_freq; in time_init()
/linux/Documentation/devicetree/bindings/timer/
H A Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
[all …]
H A Driscv,timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
[all …]
/linux/arch/microblaze/kernel/cpu/
H A Dcpuinfo.c2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2007-2009 PetaLogix
120 " - USERSPACE CAN LOCK THIS KERNEL!\n", __func__); in setup_cpuinfo()
132 /* take timebase-frequency from DTS */ in setup_cpuinfo_clk()
133 cpuinfo.cpu_clock_freq = fcpu(cpu, "timebase-frequency"); in setup_cpuinfo_clk()
139 pr_err("ERROR: CPU clock frequency not setup\n"); in setup_cpuinfo_clk()
/linux/arch/powerpc/kvm/
H A Demulate.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <asm/ppc-opcode.h>
31 pr_debug("mtDEC: %lx\n", vcpu->arch.dec); in kvmppc_emulate_dec()
32 hrtimer_try_to_cancel(&vcpu->arch.dec_timer); in kvmppc_emulate_dec()
41 if (vcpu->arch.dec == 0) in kvmppc_emulate_dec()
46 * The decrementer ticks at the same rate as the timebase, so in kvmppc_emulate_dec()
51 dec_time = vcpu->arch.dec; in kvmppc_emulate_dec()
53 * Guest timebase ticks at the same frequency as host timebase. in kvmppc_emulate_dec()
54 * So use the host timebase calculations for decrementer emulation. in kvmppc_emulate_dec()
58 hrtimer_start(&vcpu->arch.dec_timer, in kvmppc_emulate_dec()
[all …]
/linux/arch/riscv/boot/dts/sifive/
H A Dhifive-unleashed-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 #include "fu540-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pwm/pwm.h>
9 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
14 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
18 stdout-path = "serial0";
22 timebase-frequency = <RTCCLK_FREQ>;
[all …]
/linux/drivers/watchdog/
H A Dof_xilinx_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2013 - 2014 Xilinx, Inc.
24 #define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */
54 ret = clk_enable(xdev->clk); in xilinx_wdt_start()
56 dev_err(wdd->parent, "Failed to enable clock\n"); in xilinx_wdt_start()
60 spin_lock(&xdev->spinlock); in xilinx_wdt_start()
63 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); in xilinx_wdt_start()
67 xdev->base + XWT_TWCSR0_OFFSET); in xilinx_wdt_start()
69 iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET); in xilinx_wdt_start()
71 spin_unlock(&xdev->spinlock); in xilinx_wdt_start()
[all …]
/linux/tools/testing/selftests/powerpc/benchmarks/
H A Dnull_syscall.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009-2015 Anton Blanchard, IBM
74 /* Try to get out of low power/low frequency mode */ in get_proc_frequency()
84 if (strncmp(line, "timebase", 8) == 0) { in get_proc_frequency()
99 /* Find fastest clock frequency */ in get_proc_frequency()
109 override = getenv("FREQUENCY"); in get_proc_frequency()
146 elapsed_ns = (tv_now.tv_sec - tv_start.tv_sec) * 1000000000ULL + in main()
147 (tv_now.tv_nsec - tv_start.tv_nsec); in main()
148 elapsed_tb = tb_now - tb_start; in main()

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