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/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a75/
H A Dpipeline.json21 "PublicDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy",
24 "BriefDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy"
27 …for which all slots in the load-store issue queue are busy. This event counts the cycles where all…
30 …for which all slots in the load-store issue queue are busy. This event counts the cycles where all…
33 …ch all slots in the data processing issue queue are busy. This event counts the cycles where all s…
36 …ch all slots in the data processing issue queue are busy. This event counts the cycles where all s…
39 …cDescription": "Duration for which all slots in the data engine issue queue are busy. This event i…
42 …fDescription": "Duration for which all slots in the data engine issue queue are busy. This event i…
/freebsd/lib/libpmc/pmu-events/arch/x86/elkhartlake/
H A Dpipeline.json109-speculative execution path is known. The branch prediction unit (BPU) predicts the target address…
174 …e core frequency may change from time to time. For this reason this event may have a changing rati…
186 …e core frequency may change from time to time. For this reason this event may have a changing rati…
197 …ncy changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC)…
208 …ncy changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC)…
219 …ncy changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC)…
267 …ber of machine clears including memory ordering, memory disambiguation, self-modifying code, page …
277 …"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend …
284slots that were not consumed by the backend because allocation is stalled due to a mispredicted ju…
289 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
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/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A Dpipeline.json109-speculative execution path is known. The branch prediction unit (BPU) predicts the target address…
185 …e core frequency may change from time to time. For this reason this event may have a changing rati…
197 …e core frequency may change from time to time. For this reason this event may have a changing rati…
208 …ncy changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC)…
219 …ncy changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC)…
230 …ncy changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC)…
343 …ounts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stor…
365 …"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend …
372slots that were not consumed by the backend because allocation is stalled due to a mispredicted ju…
377 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…
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/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-scc-qmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-sc
[all...]
H A Dfsl,qe-ucc-qmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
19 - enum:
20 - fsl,mpc8321-ucc-qmc
21 - const: fsl,qe-ucc-qmc
25 - description: UCC (Unified communication controller) register base
26 - description: Dual port ram base
[all …]
H A Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
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H A Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
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H A Dfsl,ucc-hdlc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: High-Level Data Link Control(HDLC)
12 - Frank Li <Frank.Li@nxp.com>
16 const: fsl,ucc-hdlc
24 cell-index:
27 rx-clock-name:
30 - pattern: "^brg([0-9]|1[0-6])$"
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/freebsd/share/man/man4/
H A Dng_hci.41 .\" Copyright (c) 2001-2002 Maksim Yevmenkin <m_evmenkin@yahoo.com>
44 Bluetooth is a short-range radio link intended to replace the cable(s)
59 The Bluetooth system provides a point-to-point connection (only two
60 Bluetooth units involved), or a point-to-multipoint connection.
61 In the point-to-multipoint connection,
68 In addition, many more slaves can remain locked to the master in a so-called
79 in different piconets on a time-division multiplex basis.
81 The piconets shall not be frequency-synchronized.
83 .Ss Time Slots
84 The channel is divided into time slots, each 625 usec in length.
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H A Dumass.435 .Bd -ragged -offset indent
42 module at boot time, place the following line in
44 .Bd -literal -offset indent
75 .Bd -literal -offset indent
85 .Bd -literal -offset indent
92 Rescan all slots on a multi-slot flash reader, where the slots map to separate
94 Typically only the first slot will be enabled at boot time.
95 This assumes that the flash reader is the first SCSI bus in the system and has 4 slots.
106 .An -nosplit
H A Dnetmap.41 .\" Copyright (c) 2011-2014 Matteo Landi, Luigi Rizzo, Universita` di Pisa
45 .Bl -tag -width XXXX
51 implementing a very fast and modular in-kernel software switch/dataplane;
72 35-40 Mpps on 40 Gbit/s NICs (limited by the hardware);
79 which uses unmodified device drivers and is 3-5 times faster than
98 supports both non-blocking I/O through
145 the rings, and possibly implement zero-copy forwarding
186 .Bl -tag -width XXXX
195 Both SSS and PPP have the form [0-9a-zA-Z_]+ , the string
208 Non-blocking I/O is done with special
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/freebsd/lib/libpmc/pmu-events/arch/x86/goldmont/
H A Dpipeline.json180 …e core frequency may change from time to time. For this reason this event may have a changing rati…
207 …nge from time. This event is not affected by core frequency changes but counts as if the core is …
245 …S records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.",
249 "BriefDescription": "Unfilled issue slots per cycle",
254 …"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by th…
258 "BriefDescription": "Unfilled issue slots per cycle to recover",
263slots per core cycle that were not consumed by the backend because allocation is stalled waiting f…
268 … "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend",
273 …ssue slots per core cycle that were not consumed because of a full resource in the backend. Inclu…
306 …, but did not occur because the store data was not available at the right time. The forward might…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmontplus/
H A Dpipeline.json199 …e core frequency may change from time to time. For this reason this event may have a changing rati…
233 …nge from time. This event is not affected by core frequency changes but counts as if the core is …
280 …S records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.",
284 "BriefDescription": "Instructions retired - using Reduced Skid PEBS feature",
294 "BriefDescription": "Unfilled issue slots per cycle",
301 …"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by th…
305 "BriefDescription": "Unfilled issue slots per cycle to recover",
312slots per core cycle that were not consumed by the backend because allocation is stalled waiting f…
317 … "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend",
324 …ssue slots per core cycle that were not consumed because of a full resource in the backend. Inclu…
[all …]
/freebsd/sys/contrib/vchiq/interface/vchi/
H A Dvchi_cfg.h2 * Copyright (c) 2010-2012 Broadcom. All rights reserved.
13 * 3. The names of the above-listed copyright holders may not be used
43 /* Really determined by the message driver, and should be available from a run-time call. */
54 /* Really determined by the message driver, and should be available from a run-time call. */
77 * 1 for host-app, 1 for VMCS, and these are hooked together by a loopback MPHI VCFW
83 /* How many services can we open per connection? Extending this doesn't cost processing time, just …
99 /* How many receive slots do we use. This times VCHI_MAX_MSG_SIZE gives the effective
109 /* Do we utilise overrun facility for receive message slots? Can aid peer transmit
114 /* How many transmit slots do we use. Generally don't need many, as the hardware driver
120 /* If a service has held or queued received messages in VCHI_XOFF_THRESHOLD or more slots,
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/freebsd/share/man/man9/
H A Dosd.9110 run-time with any kernel data structure which has been suitably modified for use
113 The one-off modification required involves embedding a
136 and provide a high-level grouping for slots to be registered under.
148 The function may sleep and therefore cannot be called from a non-sleepable
152 argument specifies which high-level type grouping from
176 The function may sleep and therefore cannot be called from a non-sleepable
180 argument specifies which high-level type grouping from
197 argument specifies which high-level type grouping from
223 that is internal-use memory previously allocated via
233 argument specifies which high-level type grouping from
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/freebsd/sys/netpfil/ipfw/
H A Ddn_sched_qfq.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
73 * We use the base-0 version __fls() to match the description in
89 return fls(word) - 1; in __fls()
125 /*-------------------------------------------*/
128 Virtual time computations.
140 ^.__grp->index = 0
141 *.__grp->slot_shift
158 The per-scheduler-instance data contain all the data structures
163 * Maximum number of consecutive slots occupied by backlogged classes
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/freebsd/lib/libpmc/pmu-events/arch/x86/sapphirerapids/
H A Dpipeline.json35 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
214 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
238 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
245 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
281 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
286 …Description": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more…
292 …tion": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more…
297 …Description": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less…
303 …tion": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less…
367 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
[all …]
/freebsd/sys/net80211/
H A Dieee80211_tdma.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2007-2009 Intel Corporation
32 * TDMA-mode implementation definitions.
40 #define TDMA_MAXSLOTS 2 /* max slots/sta's */
71 uint8_t tdma_bintval; /* beacon interval (slots) */
73 uint8_t tdma_inuse[1]; /* mask of slots in use */
74 uint8_t tdma_active[1]; /* mask of active slots */
77 struct timeval tdma_lastprint; /* time of last rate-limited printf */
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/freebsd/tools/tools/netmap/
H A Dpkt-gen.81 .\" Copyright (c) 2016, George V. Neville-Neil
30 .Nm pkt-gen
34 .Bl -item -compact
43 .Op Fl d Ar dst_ip[:port[-dst_ip:port]]
44 .Op Fl s Ar src_ip[:port[-src_ip:port]]
65 .Bl -tag -width Ds
90 for client-side ping-pong operation, and
92 for server-side ping-pong operation.
108 is the number of ping-pong transactions.
111 If passed a second time, use random sizes larger or equal than the
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/freebsd/lib/libpmc/pmu-events/arch/x86/icelake/
H A Dpipeline.json10 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
158 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
182 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX …
189 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE…
248 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
259 …but has the same incrementing frequency as the time stamp counter. This event can approximate elap…
282time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For th…
294 …nge from time to time due to power or thermal throttling. For this reason, this event may have a c…
450 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
468 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/tigerlake/
H A Dpipeline.json10 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
156 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
180 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX …
187 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE…
244 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
254 …but has the same incrementing frequency as the time stamp counter. This event can approximate elap…
275time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For th…
286 …nge from time to time due to power or thermal throttling. For this reason, this event may have a c…
452 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
468 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Ddavinci-mcasp-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/davinci-mcasp-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jayesh Choudhary <j-choudhary@ti.com>
15 - ti,dm646x-mcasp-audio
16 - ti,da830-mcasp-audio
17 - ti,am33xx-mcasp-audio
18 - ti,dra7-mcasp-audio
19 - ti,omap4-mcasp-audio
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmax77620.txt4 -------------------
5 - compatible: Must be one of
9 - reg: I2C device address.
12 -------------------
13 - interrupts: The interrupt on the parent the controller is
15 - interrupt-controller: Marks the device node as an interrupt controller.
16 - #interrupt-cells: is <2> and their usage is compliant to the 2 cells
17 variant of <../interrupt-controller/interrupts.txt>
19 are defined at dt-bindings/mfd/max77620.h.
21 - system-power-controller: Indicates that this PMIC is controlling the
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/icelakex/
H A Dpipeline.json10 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
158 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
182 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX …
189 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE…
248 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
259 …but has the same incrementing frequency as the time stamp counter. This event can approximate elap…
282time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For th…
294 …nge from time to time due to power or thermal throttling. For this reason, this event may have a c…
450 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
468 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
[all …]
/freebsd/sys/netinet/
H A Dtcp_hpts.c1 /*-
2 * Copyright (c) 2016-2018 Netflix, Inc.
40 * be used to call tcp_output() of a transport stack at some time in the future.
43 * slot is the time from now that the stack wants to be called but it
58 * to prevent output processing until the time alotted has gone by.
93 * knows how to take the input queue of packets from tp->t_inqueue
119 #include <sys/time.h>
162 * defines the time in 10 usec increments (102400 x 10).
163 * This gives a range of 10usec - 1024ms to place
166 * when seeing the remainder will re-insert the
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