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/linux/drivers/gpu/drm/xe/
H A Dxe_pcode.c33 static int pcode_mailbox_status(struct xe_tile *tile) in pcode_mailbox_status() argument
45 err = xe_mmio_read32(&tile->mmio, PCODE_MAILBOX) & PCODE_ERROR_MASK; in pcode_mailbox_status()
60 drm_err(&tile_to_xe(tile)->drm, "PCODE Mailbox failed: %d %s", in __pcode_mailbox_rw()
70 static int __pcode_mailbox_rw(struct xe_tile *tile, u32 mbox, u32 *data0, u32 *data1, in __pcode_mailbox_rw()
74 struct xe_mmio *mmio = &tile->mmio; in __pcode_mailbox_rw()
77 if (tile_to_xe(tile)->info.skip_pcode) in __pcode_mailbox_rw()
98 return pcode_mailbox_status(tile); in pcode_mailbox_rw()
101 static int pcode_mailbox_rw(struct xe_tile *tile, u32 mbox, u32 *data0, u32 *data1, in xe_pcode_write_timeout() argument
105 if (tile_to_xe(tile)->info.skip_pcode) in xe_pcode_write_timeout()
108 lockdep_assert_held(&tile in xe_pcode_write_timeout()
58 __pcode_mailbox_rw(struct xe_tile * tile,u32 mbox,u32 * data0,u32 * data1,unsigned int timeout_ms,bool return_data,bool atomic) __pcode_mailbox_rw() argument
89 pcode_mailbox_rw(struct xe_tile * tile,u32 mbox,u32 * data0,u32 * data1,unsigned int timeout_ms,bool return_data,bool atomic) pcode_mailbox_rw() argument
112 xe_pcode_write64_timeout(struct xe_tile * tile,u32 mbox,u32 data0,u32 data1,int timeout) xe_pcode_write64_timeout() argument
123 xe_pcode_read(struct xe_tile * tile,u32 mbox,u32 * val,u32 * val1) xe_pcode_read() argument
134 pcode_try_request(struct xe_tile * tile,u32 mbox,u32 request,u32 reply_mask,u32 reply,u32 * status,bool atomic,int timeout_us,bool locked) pcode_try_request() argument
181 xe_pcode_request(struct xe_tile * tile,u32 mbox,u32 request,u32 reply_mask,u32 reply,int timeout_base_ms) xe_pcode_request() argument
242 xe_pcode_init_min_freq_table(struct xe_tile * tile,u32 min_gt_freq,u32 max_gt_freq) xe_pcode_init_min_freq_table() argument
285 struct xe_tile *tile = xe_device_get_root_tile(xe); xe_pcode_ready() local
320 xe_pcode_init(struct xe_tile * tile) xe_pcode_init() argument
346 struct xe_tile *tile = xe_device_get_root_tile(xe); intel_pcode_read() local
354 struct xe_tile *tile = xe_device_get_root_tile(xe); intel_pcode_write_timeout() local
363 struct xe_tile *tile = xe_device_get_root_tile(xe); intel_pcode_request() local
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H A Dxe_irq.c49 drm_WARN(&mmio->tile->xe->drm, 1, in assert_iir_is_zero()
62 static void unmask_and_enable(struct xe_tile *tile, u32 irqregs, u32 bits) in unmask_and_enable() argument
64 struct xe_mmio *mmio = &tile->mmio; in unmask_and_enable()
80 static void mask_and_disable(struct xe_tile *tile, u32 irqregs) in mask_and_disable() argument
82 struct xe_mmio *mmio = &tile->mmio; in mask_and_disable()
324 static struct xe_gt *pick_engine_gt(struct xe_tile *tile, in gt_irq_handler()
328 struct xe_device *xe = tile_to_xe(tile); in gt_irq_handler()
331 return tile->primary_gt; in gt_irq_handler()
336 return tile->media_gt; in gt_irq_handler()
342 return tile in gt_irq_handler()
280 pick_engine_gt(struct xe_tile * tile,enum xe_engine_class class,unsigned int instance) pick_engine_gt() argument
308 gt_irq_handler(struct xe_tile * tile,u32 master_ctl,unsigned long * intr_dw,u32 * identity) gt_irq_handler() argument
371 struct xe_tile *tile = xe_device_get_root_tile(xe); xelp_irq_handler() local
433 struct xe_tile *tile; dg1_irq_handler() local
494 gt_irq_reset(struct xe_tile * tile) gt_irq_reset() argument
544 xelp_irq_reset(struct xe_tile * tile) xelp_irq_reset() argument
556 dg1_irq_reset(struct xe_tile * tile) dg1_irq_reset() argument
569 dg1_irq_reset_mstr(struct xe_tile * tile) dg1_irq_reset_mstr() argument
578 struct xe_tile *tile; vf_irq_reset() local
598 struct xe_tile *tile; xe_irq_reset() local
633 struct xe_tile *tile; vf_irq_postinstall() local
652 struct xe_tile *tile; xe_irq_postinstall() local
678 struct xe_tile *tile; vf_mem_irq_handler() local
857 struct xe_tile *tile; xe_irq_msix_default_hwe_handler() local
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H A Dxe_pt.c59 static u64 __xe_pt_empty_pte(struct xe_tile *tile, struct xe_vm *vm, in __xe_pt_empty_pte() argument
62 struct xe_device *xe = tile_to_xe(tile); in __xe_pt_empty_pte()
64 u8 id = tile->id; in __xe_pt_empty_pte()
88 * @tile: The tile to create for.
101 struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_tile *tile, in xe_pt_create() argument
119 bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) | in xe_pt_create()
128 bo = xe_bo_create_pin_map(vm->xe, tile, vm, SZ_4K, in xe_pt_create()
141 xe_tile_assert(tile, level <= XE_VM_MAX_LEVEL); in xe_pt_create()
154 * @tile: The tile the scratch pagetable of which to use.
158 * Populate the page-table bo of @pt with entries pointing into the tile's
[all …]
H A Dxe_tile_sysfs.c27 struct xe_tile *tile = arg; in tile_sysfs_fini() local
29 kobject_put(tile->sysfs); in tile_sysfs_fini()
32 int xe_tile_sysfs_init(struct xe_tile *tile) in xe_tile_sysfs_init() argument
34 struct xe_device *xe = tile_to_xe(tile); in xe_tile_sysfs_init()
44 kt->tile = tile; in xe_tile_sysfs_init()
46 err = kobject_add(&kt->base, &dev->kobj, "tile%d", tile->id); in xe_tile_sysfs_init()
50 tile->sysfs = &kt->base; in xe_tile_sysfs_init()
52 err = xe_vram_freq_sysfs_init(tile); in xe_tile_sysfs_init()
56 return devm_add_action_or_reset(xe->drm.dev, tile_sysfs_fini, tile); in xe_tile_sysfs_init()
H A Dxe_ggtt.c109 struct xe_tile *tile = ggtt->tile; in ggtt_update_access_counter() local
113 if (tile->primary_gt && XE_GT_WA(tile->primary_gt, 22019338487)) { in ggtt_update_access_counter()
114 affected_gt = tile->primary_gt; in ggtt_update_access_counter()
118 xe_tile_assert(tile, IS_DGFX(tile_to_xe(tile))); in ggtt_update_access_counter()
120 affected_gt = tile->media_gt; in ggtt_update_access_counter()
124 xe_tile_assert(tile, !IS_DGFX(tile_to_xe(tile))); in ggtt_update_access_counter()
142 xe_tile_assert(ggtt->tile, !(addr & XE_PTE_MASK)); in xe_ggtt_set_pte()
143 xe_tile_assert(ggtt->tile, addr < ggtt->size); in xe_ggtt_set_pte()
156 xe_tile_assert(ggtt->tile, !(addr & XE_PTE_MASK)); in xe_ggtt_get_pte()
157 xe_tile_assert(ggtt->tile, addr < ggtt->size); in xe_ggtt_get_pte()
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H A Dxe_vram.c204 * @tile: tile to get info for
218 * NOTE: multi-tile bases will include the tile offset.
221 static int tile_vram_size(struct xe_tile *tile, u64 *vram_size, in tile_vram_size() argument
224 struct xe_device *xe = tile_to_xe(tile); in tile_vram_size()
225 struct xe_gt *gt = tile->primary_gt; in tile_vram_size()
235 for_each_if(t->id < tile->id) in tile_vram_size()
238 *tile_size = xe_tile_sriov_vf_lmem(tile); in tile_vram_size()
250 reg = xe_mmio_read32(&tile->mmio, SG_TILE_ADDR_RANGE(tile->id)); in tile_vram_size()
262 offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE); in tile_vram_size()
265 /* remove the tile offset so we have just the available size */ in tile_vram_size()
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H A Dxe_pcode.h15 void xe_pcode_init(struct xe_tile *tile);
18 int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq,
20 int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1);
21 int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val,
23 int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0,
26 #define xe_pcode_write(tile, mbox, val) \ argument
27 xe_pcode_write_timeout(tile, mbox, val, 1)
29 int xe_pcode_request(struct xe_tile *tile, u32 mbox, u32 request,
H A Dxe_bo_evict.c162 struct xe_tile *tile; in xe_bo_evict_all() local
181 for_each_tile(tile, xe, id) in xe_bo_evict_all()
182 xe_tile_migrate_wait(tile); in xe_bo_evict_all()
201 struct xe_tile *tile; in xe_bo_restore_and_map_ggtt() local
204 for_each_tile(tile, xe_bo_device(bo), id) { in xe_bo_restore_and_map_ggtt()
205 if (tile != bo->tile && !(bo->flags & XE_BO_FLAG_GGTTx(tile))) in xe_bo_restore_and_map_ggtt()
208 xe_ggtt_map_bo_unlocked(tile->mem.ggtt, bo); in xe_bo_restore_and_map_ggtt()
245 struct xe_tile *tile; in xe_bo_restore_late() local
252 for_each_tile(tile, xe, id) in xe_bo_restore_late()
253 xe_tile_migrate_wait(tile); in xe_bo_restore_late()
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H A Dxe_tile_sysfs_types.h14 * struct kobj_tile - A tile's kobject struct that connects the kobject
15 * and the TILE
18 * TILE needs to be addressed on a given sysfs call.
23 /** @tile: A pointer to the tile itself */
24 struct xe_tile *tile; member
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dnv20.c31 u32 flags, struct nvkm_fb_tile *tile) in nv20_fb_tile_init() argument
33 tile->addr = 0x00000001 | addr; in nv20_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv20_fb_tile_init()
35 tile->pitch = pitch; in nv20_fb_tile_init()
37 fb->func->tile.comp(fb, i, size, flags, tile); in nv20_fb_tile_init()
38 tile->addr |= 2; in nv20_fb_tile_init()
44 struct nvkm_fb_tile *tile) in nv20_fb_tile_comp() argument
48 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv20_fb_tile_comp()
49 if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ in nv20_fb_tile_comp()
50 else tile->zcomp = 0x04000000; /* Z24S8 */ in nv20_fb_tile_comp()
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H A Dnv30.c31 u32 flags, struct nvkm_fb_tile *tile) in nv30_fb_tile_init() argument
35 tile->addr = (0 << 4); in nv30_fb_tile_init()
37 if (fb->func->tile.comp) /* z compression */ in nv30_fb_tile_init()
38 fb->func->tile.comp(fb, i, size, flags, tile); in nv30_fb_tile_init()
39 tile->addr = (1 << 4); in nv30_fb_tile_init()
42 tile->addr |= 0x00000001; /* enable */ in nv30_fb_tile_init()
43 tile->addr |= addr; in nv30_fb_tile_init()
44 tile->limit = max(1u, addr + size) - 1; in nv30_fb_tile_init()
45 tile->pitch = pitch; in nv30_fb_tile_init()
50 struct nvkm_fb_tile *tile) in nv30_fb_tile_comp() argument
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H A Dnv10.c31 u32 flags, struct nvkm_fb_tile *tile) in nv10_fb_tile_init() argument
33 tile->addr = 0x80000000 | addr; in nv10_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv10_fb_tile_init()
35 tile->pitch = pitch; in nv10_fb_tile_init()
39 nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_fini() argument
41 tile->addr = 0; in nv10_fb_tile_fini()
42 tile->limit = 0; in nv10_fb_tile_fini()
43 tile->pitch = 0; in nv10_fb_tile_fini()
44 tile->zcomp = 0; in nv10_fb_tile_fini()
48 nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_prog() argument
[all …]
H A Dnv35.c31 struct nvkm_fb_tile *tile) in nv35_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv35_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ in nv35_fb_tile_comp()
37 else tile->zcomp |= 0x08000000; /* Z24S8 */ in nv35_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv35_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13; in nv35_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv35_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv35_fb_tile_comp,
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H A Dnv36.c31 struct nvkm_fb_tile *tile) in nv36_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv36_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ in nv36_fb_tile_comp()
37 else tile->zcomp |= 0x20000000; /* Z24S8 */ in nv36_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv36_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14; in nv36_fb_tile_comp()
41 tile->zcomp |= 0x80000000; in nv36_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv36_fb_tile_comp,
[all …]
H A Dnv44.c31 u32 flags, struct nvkm_fb_tile *tile) in nv44_fb_tile_init() argument
33 tile->addr = 0x00000001; /* mode = vram */ in nv44_fb_tile_init()
34 tile->addr |= addr; in nv44_fb_tile_init()
35 tile->limit = max(1u, addr + size) - 1; in nv44_fb_tile_init()
36 tile->pitch = pitch; in nv44_fb_tile_init()
40 nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv44_fb_tile_prog() argument
43 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv44_fb_tile_prog()
44 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv44_fb_tile_prog()
45 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv44_fb_tile_prog()
60 .tile.regions = 12,
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H A Dnv40.c31 struct nvkm_fb_tile *tile) in nv40_fb_tile_comp() argument
36 !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 8); in nv40_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
56 .tile.regions = 8,
57 .tile.init = nv30_fb_tile_init,
58 .tile.comp = nv40_fb_tile_comp,
59 .tile.fini = nv20_fb_tile_fini,
[all …]
H A Dnv25.c31 struct nvkm_fb_tile *tile) in nv25_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv25_fb_tile_comp()
36 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ in nv25_fb_tile_comp()
37 else tile->zcomp = 0x00200000; /* Z24S8 */ in nv25_fb_tile_comp()
38 tile->zcomp |= tile->tag->offset; in nv25_fb_tile_comp()
40 tile->zcomp |= 0x01000000; in nv25_fb_tile_comp()
48 .tile.regions = 8,
49 .tile.init = nv20_fb_tile_init,
50 .tile.comp = nv25_fb_tile_comp,
51 .tile.fini = nv20_fb_tile_fini,
[all …]
H A Dnv46.c31 u32 flags, struct nvkm_fb_tile *tile) in nv46_fb_tile_init() argument
34 if (!(flags & 4)) tile->addr = (0 << 3); in nv46_fb_tile_init()
35 else tile->addr = (1 << 3); in nv46_fb_tile_init()
37 tile->addr |= 0x00000001; /* mode = vram */ in nv46_fb_tile_init()
38 tile->addr |= addr; in nv46_fb_tile_init()
39 tile->limit = max(1u, addr + size) - 1; in nv46_fb_tile_init()
40 tile->pitch = pitch; in nv46_fb_tile_init()
46 .tile.regions = 15,
47 .tile.init = nv46_fb_tile_init,
48 .tile.fini = nv20_fb_tile_fini,
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H A Dnv41.c30 nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv41_fb_tile_prog() argument
33 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv41_fb_tile_prog()
34 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv41_fb_tile_prog()
35 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv41_fb_tile_prog()
37 nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp); in nv41_fb_tile_prog()
50 .tile.regions = 12,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv40_fb_tile_comp,
53 .tile.fini = nv20_fb_tile_fini,
54 .tile.prog = nv41_fb_tile_prog,
H A Dbase.c35 nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_fini() argument
37 fb->func->tile.fini(fb, region, tile); in nvkm_fb_tile_fini()
42 u32 pitch, u32 flags, struct nvkm_fb_tile *tile) in nvkm_fb_tile_init() argument
44 fb->func->tile.init(fb, region, addr, size, pitch, flags, tile); in nvkm_fb_tile_init()
48 nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_prog() argument
51 if (fb->func->tile.prog) { in nvkm_fb_tile_prog()
52 fb->func->tile.prog(fb, region, tile); in nvkm_fb_tile_prog()
201 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_init()
202 fb->func->tile.prog(fb, i, &fb->tile.region[i]); in nvkm_fb_init()
240 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_dtor()
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/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A Dcache.json67 …ounts the loads retired that get the data from the other core in the same tile in M state (Precise…
135 …data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. …
145 …ata forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. …
155 … data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
165 …r responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
175 …esponses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
185 … responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
195 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in E…
205 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in F…
215 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in M…
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv44.c31 nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv44_gr_tile() argument
44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
56 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv44_gr_tile()
57 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv44_gr_tile()
58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
[all …]
/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_cr_defs_client.h64 * X1 MacroTile boundary, left tile X for second column of macrotiles (16MT mode) - 32 pixels across
65 * tile
70 * X2 MacroTile boundary, left tile X for third(16MT) column of macrotiles - 32 pixels across tile
75 * X3 MacroTile boundary, left tile X for fourth column of macrotiles (16MT) - 32 pixels across tile
85 * X1 MacroTile boundary, ltop tile Y for second column of macrotiles (16MT mode) - 32 pixels tile
91 * X2 MacroTile boundary, top tile Y for third(16MT) column of macrotiles - 32 pixels tile height
96 * X3 MacroTile boundary, top tile Y for fourth column of macrotiles (16MT) - 32 pixels tile height
110 * Maximum Y tile address visible on screen, 32 pixel tile height, 16Kx16K max screen size
115 * Maximum X tile address visible on screen, 32 pixel tile width, 16Kx16K max screen size
/linux/drivers/hid/
H A Dhid-picolcd_fb.c22 * each. Each tile has 8x64 pixel, each data byte representing
23 * a 1-bit wide vertical line of the tile.
25 * The display can be updated at a tile granularity.
29 * | Tile 1 | Tile 1 | Tile 1 | Tile 1 |
31 * | Tile 2 | Tile 2 | Tile 2 | Tile 2 |
35 * | Tile 8 | Tile 8 | Tile 8 | Tile 8 |
89 /* Send a given tile to PicoLCD */
91 int chip, int tile) in picolcd_fb_send_tile() argument
114 hid_set_field(report1->field[0], 4, 0xb8 | tile); in picolcd_fb_send_tile()
127 tdata = vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_send_tile()
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/linux/arch/arm/mach-versatile/
H A DKconfig129 bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 bool "Integrator/CTB36 (ARM1136JF-S) core tile"
178 the ARM926EJ-S core tile, while on an ARMv6/v7 kernel, at least
180 core tile options should be enabled.
183 bool "Support ARM1136J(F)-S Tile"
187 Enable support for the ARM1136 tile fitted to the
191 bool "Support ARM1176JZ(F)-S Tile"
194 Enable support for the ARM1176 tile fitted to the
198 bool "Support Multicore Cortex-A9 Tile"
201 Enable support for the Cortex-A9MPCore tile fitted to the
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