| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_tile.c | 22 * DOC: Multi-tile Design
24 * Different vendors use the term "tile" a bit differently, but in the Intel
25 * world, a 'tile' is pretty close to what most people would think of as being
27 * that's what is referred to as a "multi-tile device." In such cases, pretty
28 * much all hardware is replicated per-tile, although certain responsibilities
30 * solely by the "root tile." A multi-tile platform takes care of tying the
32 * are forwarded to the root tile, the per-tile vram is combined into a single
36 * the subset of a GPU/tile that is responsible for implementing graphics
41 * Historically most Intel devices were single-tile devices that contained a
42 * single GT. PVC is an example of an Intel platform built on a multi-tile
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| H A D | xe_pcode.c | 32 static int pcode_mailbox_status(struct xe_tile *tile) in pcode_mailbox_status() argument
47 err = xe_mmio_read32(&tile->mmio, PCODE_MAILBOX) & PCODE_ERROR_MASK; in pcode_mailbox_status()
49 drm_err(&tile_to_xe(tile)->drm, "PCODE Mailbox failed: %d %s", err, in pcode_mailbox_status()
57 static int __pcode_mailbox_rw(struct xe_tile *tile, u32 mbox, u32 *data0, u32 *data1, in __pcode_mailbox_rw() argument
61 struct xe_mmio *mmio = &tile->mmio; in __pcode_mailbox_rw()
64 if (tile_to_xe(tile)->info.skip_pcode) in __pcode_mailbox_rw()
85 return pcode_mailbox_status(tile); in __pcode_mailbox_rw()
88 static int pcode_mailbox_rw(struct xe_tile *tile, u32 mbox, u32 *data0, u32 *data1, in pcode_mailbox_rw() argument
92 if (tile_to_xe(tile)->info.skip_pcode) in pcode_mailbox_rw()
95 lockdep_assert_held(&tile->pcode.lock); in pcode_mailbox_rw()
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| H A D | xe_irq.c | 45 drm_WARN(&mmio->tile->xe->drm, 1, in assert_iir_is_zero()
58 static void unmask_and_enable(struct xe_tile *tile, u32 irqregs, u32 bits) in unmask_and_enable() argument
60 struct xe_mmio *mmio = &tile->mmio; in unmask_and_enable()
76 static void mask_and_disable(struct xe_tile *tile, u32 irqregs) in mask_and_disable() argument
78 struct xe_mmio *mmio = &tile->mmio; in mask_and_disable()
267 static struct xe_gt *pick_engine_gt(struct xe_tile *tile, in pick_engine_gt() argument
271 struct xe_device *xe = tile_to_xe(tile); in pick_engine_gt()
274 return tile->primary_gt; in pick_engine_gt()
279 return tile->media_gt; in pick_engine_gt()
285 return tile->media_gt; in pick_engine_gt()
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| H A D | xe_vram.c | 201 * @tile: tile to get info for
215 * NOTE: multi-tile bases will include the tile offset.
218 static int tile_vram_size(struct xe_tile *tile, u64 *vram_size, in tile_vram_size() argument
221 struct xe_device *xe = tile_to_xe(tile); in tile_vram_size()
222 struct xe_gt *gt = tile->primary_gt; in tile_vram_size()
233 for_each_if(t->id < tile->id) in tile_vram_size()
261 offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE); in tile_vram_size()
264 /* remove the tile offset so we have just the available size */ in tile_vram_size()
275 struct xe_tile *tile; in vram_fini() local
283 for_each_tile(tile, xe, id) in vram_fini()
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| H A D | xe_mmio.c | 29 struct xe_tile *tile; in tiles_fini() local
32 for_each_remote_tile(tile, xe, id) in tiles_fini()
33 tile->mmio.regs = NULL; in tiles_fini()
37 * On multi-tile devices, partition the BAR space for MMIO on each tile,
39 * tile_mmio_size contains both the tile's 4MB register space, as well as
57 struct xe_tile *tile; in mmio_multi_tile_setup() local
62 * Nothing to be done as tile 0 has already been setup earlier with the in mmio_multi_tile_setup()
68 /* Possibly override number of tile based on configuration register */ in mmio_multi_tile_setup()
75 * Although the per-tile mmio regs are not yet initialized, this in mmio_multi_tile_setup()
76 * is fine as it's going to the root tile's mmio, that's in mmio_multi_tile_setup()
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| H A D | xe_pt.c | 59 static u64 __xe_pt_empty_pte(struct xe_tile *tile, struct xe_vm *vm, in __xe_pt_empty_pte() argument
62 struct xe_device *xe = tile_to_xe(tile); in __xe_pt_empty_pte()
64 u8 id = tile->id; in __xe_pt_empty_pte()
88 * @tile: The tile to create for.
100 struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_tile *tile, in xe_pt_create() argument
118 bo = xe_bo_create_pin_map(vm->xe, tile, vm, SZ_4K, in xe_pt_create()
120 XE_BO_FLAG_VRAM_IF_DGFX(tile) | in xe_pt_create()
135 xe_tile_assert(tile, level <= XE_VM_MAX_LEVEL); in xe_pt_create()
148 * @tile: The tile the scratch pagetable of which to use.
152 * Populate the page-table bo of @pt with entries pointing into the tile's
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| H A D | xe_tile_sysfs.c | 27 struct xe_tile *tile = arg; in tile_sysfs_fini() local
29 kobject_put(tile->sysfs); in tile_sysfs_fini()
32 int xe_tile_sysfs_init(struct xe_tile *tile) in xe_tile_sysfs_init() argument
34 struct xe_device *xe = tile_to_xe(tile); in xe_tile_sysfs_init()
44 kt->tile = tile; in xe_tile_sysfs_init()
46 err = kobject_add(&kt->base, &dev->kobj, "tile%d", tile->id); in xe_tile_sysfs_init()
52 tile->sysfs = &kt->base; in xe_tile_sysfs_init()
54 err = xe_vram_freq_sysfs_init(tile); in xe_tile_sysfs_init()
58 return devm_add_action_or_reset(xe->drm.dev, tile_sysfs_fini, tile); in xe_tile_sysfs_init()
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| H A D | xe_vram_freq.c | 18 * Provides sysfs entries for vram frequency in tile
20 * device/tile#/memory/freq0/max_freq - This is maximum frequency. This value is read-only as it
23 * device/tile#/memory/freq0/min_freq - This is minimum frequency. This value is read-only as it
36 struct xe_tile *tile = dev_to_tile(dev); in max_freq_show() local
44 err = xe_pcode_read(tile, mbox, &val, NULL); in max_freq_show()
58 struct xe_tile *tile = dev_to_tile(dev); in min_freq_show() local
66 err = xe_pcode_read(tile, mbox, &val, NULL); in min_freq_show()
98 * @tile: Xe Tile object
100 * It needs to be initialized after the main tile component is ready
104 int xe_vram_freq_sysfs_init(struct xe_tile *tile) in xe_vram_freq_sysfs_init() argument
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| H A D | xe_ggtt.c | 111 struct xe_tile *tile = ggtt->tile; in ggtt_update_access_counter() local
112 struct xe_gt *affected_gt = XE_WA(tile->primary_gt, 22019338487) ? in ggtt_update_access_counter()
113 tile->primary_gt : tile->media_gt; in ggtt_update_access_counter()
115 u32 max_gtt_writes = XE_WA(ggtt->tile->primary_gt, 22019338487) ? 1100 : 63; in ggtt_update_access_counter()
131 xe_tile_assert(ggtt->tile, !(addr & XE_PTE_MASK)); in xe_ggtt_set_pte()
132 xe_tile_assert(ggtt->tile, addr < ggtt->size); in xe_ggtt_set_pte()
145 u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[XE_CACHE_WB]; in xe_ggtt_clear()
149 xe_tile_assert(ggtt->tile, start < end); in xe_ggtt_clear()
217 struct xe_device *xe = tile_to_xe(ggtt->tile); in xe_ggtt_init_early()
232 ggtt->gsm = ggtt->tile->mmio.regs + SZ_8M; in xe_ggtt_init_early()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | nv20.c | 31 u32 flags, struct nvkm_fb_tile *tile) in nv20_fb_tile_init() argument
33 tile->addr = 0x00000001 | addr; in nv20_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv20_fb_tile_init()
35 tile->pitch = pitch; in nv20_fb_tile_init()
37 fb->func->tile.comp(fb, i, size, flags, tile); in nv20_fb_tile_init()
38 tile->addr |= 2; in nv20_fb_tile_init()
44 struct nvkm_fb_tile *tile) in nv20_fb_tile_comp() argument
48 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv20_fb_tile_comp()
49 if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ in nv20_fb_tile_comp()
50 else tile->zcomp = 0x04000000; /* Z24S8 */ in nv20_fb_tile_comp()
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| H A D | nv30.c | 31 u32 flags, struct nvkm_fb_tile *tile) in nv30_fb_tile_init() argument
35 tile->addr = (0 << 4); in nv30_fb_tile_init()
37 if (fb->func->tile.comp) /* z compression */ in nv30_fb_tile_init()
38 fb->func->tile.comp(fb, i, size, flags, tile); in nv30_fb_tile_init()
39 tile->addr = (1 << 4); in nv30_fb_tile_init()
42 tile->addr |= 0x00000001; /* enable */ in nv30_fb_tile_init()
43 tile->addr |= addr; in nv30_fb_tile_init()
44 tile->limit = max(1u, addr + size) - 1; in nv30_fb_tile_init()
45 tile->pitch = pitch; in nv30_fb_tile_init()
50 struct nvkm_fb_tile *tile) in nv30_fb_tile_comp() argument
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| H A D | nv10.c | 31 u32 flags, struct nvkm_fb_tile *tile) in nv10_fb_tile_init() argument
33 tile->addr = 0x80000000 | addr; in nv10_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv10_fb_tile_init()
35 tile->pitch = pitch; in nv10_fb_tile_init()
39 nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_fini() argument
41 tile->addr = 0; in nv10_fb_tile_fini()
42 tile->limit = 0; in nv10_fb_tile_fini()
43 tile->pitch = 0; in nv10_fb_tile_fini()
44 tile->zcomp = 0; in nv10_fb_tile_fini()
48 nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_prog() argument
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| H A D | nv35.c | 31 struct nvkm_fb_tile *tile) in nv35_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv35_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ in nv35_fb_tile_comp()
37 else tile->zcomp |= 0x08000000; /* Z24S8 */ in nv35_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv35_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13; in nv35_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv35_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv35_fb_tile_comp,
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| H A D | nv36.c | 31 struct nvkm_fb_tile *tile) in nv36_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv36_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ in nv36_fb_tile_comp()
37 else tile->zcomp |= 0x20000000; /* Z24S8 */ in nv36_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv36_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14; in nv36_fb_tile_comp()
41 tile->zcomp |= 0x80000000; in nv36_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv36_fb_tile_comp,
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| H A D | nv44.c | 31 u32 flags, struct nvkm_fb_tile *tile) in nv44_fb_tile_init() argument
33 tile->addr = 0x00000001; /* mode = vram */ in nv44_fb_tile_init()
34 tile->addr |= addr; in nv44_fb_tile_init()
35 tile->limit = max(1u, addr + size) - 1; in nv44_fb_tile_init()
36 tile->pitch = pitch; in nv44_fb_tile_init()
40 nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv44_fb_tile_prog() argument
43 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv44_fb_tile_prog()
44 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv44_fb_tile_prog()
45 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv44_fb_tile_prog()
60 .tile.regions = 12,
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| H A D | nv40.c | 31 struct nvkm_fb_tile *tile) in nv40_fb_tile_comp() argument
36 !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 8); in nv40_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
56 .tile.regions = 8,
57 .tile.init = nv30_fb_tile_init,
58 .tile.comp = nv40_fb_tile_comp,
59 .tile.fini = nv20_fb_tile_fini,
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| H A D | nv25.c | 31 struct nvkm_fb_tile *tile) in nv25_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv25_fb_tile_comp()
36 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ in nv25_fb_tile_comp()
37 else tile->zcomp = 0x00200000; /* Z24S8 */ in nv25_fb_tile_comp()
38 tile->zcomp |= tile->tag->offset; in nv25_fb_tile_comp()
40 tile->zcomp |= 0x01000000; in nv25_fb_tile_comp()
48 .tile.regions = 8,
49 .tile.init = nv20_fb_tile_init,
50 .tile.comp = nv25_fb_tile_comp,
51 .tile.fini = nv20_fb_tile_fini,
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| H A D | nv46.c | 31 u32 flags, struct nvkm_fb_tile *tile) in nv46_fb_tile_init() argument
34 if (!(flags & 4)) tile->addr = (0 << 3); in nv46_fb_tile_init()
35 else tile->addr = (1 << 3); in nv46_fb_tile_init()
37 tile->addr |= 0x00000001; /* mode = vram */ in nv46_fb_tile_init()
38 tile->addr |= addr; in nv46_fb_tile_init()
39 tile->limit = max(1u, addr + size) - 1; in nv46_fb_tile_init()
40 tile->pitch = pitch; in nv46_fb_tile_init()
46 .tile.regions = 15,
47 .tile.init = nv46_fb_tile_init,
48 .tile.fini = nv20_fb_tile_fini,
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| H A D | nv41.c | 30 nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv41_fb_tile_prog() argument
33 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv41_fb_tile_prog()
34 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv41_fb_tile_prog()
35 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv41_fb_tile_prog()
37 nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp); in nv41_fb_tile_prog()
50 .tile.regions = 12,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv40_fb_tile_comp,
53 .tile.fini = nv20_fb_tile_fini,
54 .tile.prog = nv41_fb_tile_prog,
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| /linux/tools/perf/pmu-events/arch/x86/knightslanding/ |
| H A D | cache.json | 67 …ounts the loads retired that get the data from the other core in the same tile in M state (Precise…
135 …data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. …
145 …ata forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. …
155 … data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
165 …r responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
175 …esponses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
185 … responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
195 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in E…
205 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in F…
215 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in M…
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| /linux/drivers/gpu/drm/i915/gem/selftests/ |
| H A D | i915_gem_mman.c | 30 struct tile { struct
44 static u64 tiled_offset(const struct tile *tile, u64 v) in tiled_offset() argument
48 if (tile->tiling == I915_TILING_NONE) in tiled_offset()
51 y = div64_u64_rem(v, tile->stride, &x); in tiled_offset()
52 v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height; in tiled_offset()
54 if (tile->tiling == I915_TILING_X) { in tiled_offset()
55 v += y * tile->width; in tiled_offset()
56 v += div64_u64_rem(x, tile->width, &x) << tile->size; in tiled_offset()
58 } else if (tile->width == 128) { in tiled_offset()
74 switch (tile->swizzle) { in tiled_offset()
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| /linux/drivers/gpu/ipu-v3/ |
| H A D | ipu-image-convert.c | 28 * tile (but taking care to pass the full frame stride length to
30 * to convert each tile back-to-back when possible (see note below
45 * reusable temporary tile buffer and then rotating with the 8x8
61 * With rotation or flipping, tile order changes between input and
96 /* dimensions of one tile */
106 /* start Y or packed offset of this tile */
108 /* offset from start to tile in U plane, for planar formats */
110 /* offset from start to tile in V plane, for planar formats */
126 struct ipu_image_tile tile[MAX_TILES]; member
185 /* next tile to process */
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| H A D | nv44.c | 31 nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv44_gr_tile() argument
44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
56 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv44_gr_tile()
57 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv44_gr_tile()
58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
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| /linux/drivers/gpu/drm/imagination/ |
| H A D | pvr_rogue_cr_defs_client.h | 64 * X1 MacroTile boundary, left tile X for second column of macrotiles (16MT mode) - 32 pixels across
65 * tile
70 * X2 MacroTile boundary, left tile X for third(16MT) column of macrotiles - 32 pixels across tile
75 * X3 MacroTile boundary, left tile X for fourth column of macrotiles (16MT) - 32 pixels across tile
85 * X1 MacroTile boundary, ltop tile Y for second column of macrotiles (16MT mode) - 32 pixels tile
91 * X2 MacroTile boundary, top tile Y for third(16MT) column of macrotiles - 32 pixels tile height
96 * X3 MacroTile boundary, top tile Y for fourth column of macrotiles (16MT) - 32 pixels tile height
110 * Maximum Y tile address visible on screen, 32 pixel tile height, 16Kx16K max screen size
115 * Maximum X tile address visible on screen, 32 pixel tile width, 16Kx16K max screen size
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| /linux/include/uapi/linux/media/raspberrypi/ |
| H A D | pisp_be_config.h | 24 /* minimum allowed tile width anywhere in the pipeline */
26 /* minimum allowed tile width anywhere in the pipeline */
309 * @offset_x: Horizontal offset into the LSC table of this tile
310 * @offset_y: Vertical offset into the LSC table of this tile
342 * @offset_x: Horizontal offset into the CAC table of this tile
343 * @offset_y: Horizontal offset into the CAC table of this tile
581 * @offset_x: Number of pixels cropped from the left of the tile
582 * @offset_y: Number of pixels cropped from the top of the tile
583 * @width: Width of the cropped tile output
584 * @height: Height of the cropped tile output
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