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/linux/drivers/gpu/drm/xe/
H A Dxe_pcode.c33 static int pcode_mailbox_status(struct xe_tile *tile) in pcode_mailbox_status() argument
48 err = xe_mmio_read32(&tile->mmio, PCODE_MAILBOX) & PCODE_ERROR_MASK; in pcode_mailbox_status()
50 drm_err(&tile_to_xe(tile)->drm, "PCODE Mailbox failed: %d %s", err, in pcode_mailbox_status()
58 static int __pcode_mailbox_rw(struct xe_tile *tile, u32 mbox, u32 *data0, u32 *data1, in __pcode_mailbox_rw() argument
62 struct xe_mmio *mmio = &tile->mmio; in __pcode_mailbox_rw()
65 if (tile_to_xe(tile)->info.skip_pcode) in __pcode_mailbox_rw()
86 return pcode_mailbox_status(tile); in __pcode_mailbox_rw()
89 static int pcode_mailbox_rw(struct xe_tile *tile, u32 mbox, u32 *data0, u32 *data1, in pcode_mailbox_rw() argument
93 if (tile_to_xe(tile)->info.skip_pcode) in pcode_mailbox_rw()
96 lockdep_assert_held(&tile->pcode.lock); in pcode_mailbox_rw()
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H A Dxe_tile_sysfs.c27 struct xe_tile *tile = arg; in tile_sysfs_fini() local
29 kobject_put(tile->sysfs); in tile_sysfs_fini()
32 int xe_tile_sysfs_init(struct xe_tile *tile) in xe_tile_sysfs_init() argument
34 struct xe_device *xe = tile_to_xe(tile); in xe_tile_sysfs_init()
44 kt->tile = tile; in xe_tile_sysfs_init()
46 err = kobject_add(&kt->base, &dev->kobj, "tile%d", tile->id); in xe_tile_sysfs_init()
50 tile->sysfs = &kt->base; in xe_tile_sysfs_init()
52 err = xe_vram_freq_sysfs_init(tile); in xe_tile_sysfs_init()
56 return devm_add_action_or_reset(xe->drm.dev, tile_sysfs_fini, tile); in xe_tile_sysfs_init()
H A Dxe_pcode.h15 void xe_pcode_init(struct xe_tile *tile);
18 int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq,
20 int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1);
21 int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val,
23 int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0,
26 #define xe_pcode_write(tile, mbox, val) \ argument
27 xe_pcode_write_timeout(tile, mbox, val, 1)
29 int xe_pcode_request(struct xe_tile *tile, u32 mbox, u32 request,
H A Dxe_tile_sysfs_types.h14 * struct kobj_tile - A tile's kobject struct that connects the kobject
15 * and the TILE
18 * TILE needs to be addressed on a given sysfs call.
23 /** @tile: A pointer to the tile itself */
24 struct xe_tile *tile; member
H A Dxe_device_types.h81 * tile share the same map with their parent tile, but represent different
85 /** @tile: Backpointer to tile, used for tracing */
86 struct xe_tile *tile; member
116 * struct xe_tile - hardware tile structure
118 * From a driver perspective, a "tile" is effectively a complete GPU, containing
121 * Multi-tile platforms effectively bundle multiple GPUs behind a single PCI
122 * device and designate one "root" tile as being responsible for external PCI
124 * tile in a stacked layout, and PCI BAR2 exposes the local memory associated
125 * with each tile similarly. Device-wide interrupts can be enabled/disabled
126 * at the root tile, and the MSTR_TILE_INTR register will report which tiles
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H A Dxe_bo.h29 #define XE_BO_FLAG_VRAM_IF_DGFX(tile) (IS_DGFX(tile_to_xe(tile)) ? \ argument
30 XE_BO_FLAG_VRAM((tile)->mem.vram) : \
62 #define XE_BO_FLAG_GGTTx(tile) \ argument
63 (XE_BO_FLAG_GGTT0 << (tile)->id)
93 struct xe_tile *tile, struct dma_resv *resv,
97 struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_tile *tile,
103 struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_tile *tile,
107 struct xe_bo *xe_bo_create_pin_map_novm(struct xe_device *xe, struct xe_tile *tile,
110 struct xe_bo *xe_bo_create_pin_range_novm(struct xe_device *xe, struct xe_tile *tile,
114 xe_bo_create_pin_map_at_novm(struct xe_device *xe, struct xe_tile *tile,
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dnv20.c31 u32 flags, struct nvkm_fb_tile *tile) in nv20_fb_tile_init() argument
33 tile->addr = 0x00000001 | addr; in nv20_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv20_fb_tile_init()
35 tile->pitch = pitch; in nv20_fb_tile_init()
37 fb->func->tile.comp(fb, i, size, flags, tile); in nv20_fb_tile_init()
38 tile->addr |= 2; in nv20_fb_tile_init()
44 struct nvkm_fb_tile *tile) in nv20_fb_tile_comp() argument
48 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv20_fb_tile_comp()
49 if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ in nv20_fb_tile_comp()
50 else tile->zcomp = 0x04000000; /* Z24S8 */ in nv20_fb_tile_comp()
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H A Dnv30.c31 u32 flags, struct nvkm_fb_tile *tile) in nv30_fb_tile_init() argument
35 tile->addr = (0 << 4); in nv30_fb_tile_init()
37 if (fb->func->tile.comp) /* z compression */ in nv30_fb_tile_init()
38 fb->func->tile.comp(fb, i, size, flags, tile); in nv30_fb_tile_init()
39 tile->addr = (1 << 4); in nv30_fb_tile_init()
42 tile->addr |= 0x00000001; /* enable */ in nv30_fb_tile_init()
43 tile->addr |= addr; in nv30_fb_tile_init()
44 tile->limit = max(1u, addr + size) - 1; in nv30_fb_tile_init()
45 tile->pitch = pitch; in nv30_fb_tile_init()
50 struct nvkm_fb_tile *tile) in nv30_fb_tile_comp() argument
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H A Dnv10.c31 u32 flags, struct nvkm_fb_tile *tile) in nv10_fb_tile_init() argument
33 tile->addr = 0x80000000 | addr; in nv10_fb_tile_init()
34 tile->limit = max(1u, addr + size) - 1; in nv10_fb_tile_init()
35 tile->pitch = pitch; in nv10_fb_tile_init()
39 nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_fini() argument
41 tile->addr = 0; in nv10_fb_tile_fini()
42 tile->limit = 0; in nv10_fb_tile_fini()
43 tile->pitch = 0; in nv10_fb_tile_fini()
44 tile->zcomp = 0; in nv10_fb_tile_fini()
48 nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv10_fb_tile_prog() argument
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H A Dnv35.c31 struct nvkm_fb_tile *tile) in nv35_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv35_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ in nv35_fb_tile_comp()
37 else tile->zcomp |= 0x08000000; /* Z24S8 */ in nv35_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv35_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13; in nv35_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv35_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv35_fb_tile_comp,
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H A Dnv36.c31 struct nvkm_fb_tile *tile) in nv36_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv36_fb_tile_comp()
36 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ in nv36_fb_tile_comp()
37 else tile->zcomp |= 0x20000000; /* Z24S8 */ in nv36_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 6); in nv36_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14; in nv36_fb_tile_comp()
41 tile->zcomp |= 0x80000000; in nv36_fb_tile_comp()
50 .tile.regions = 8,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv36_fb_tile_comp,
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H A Dnv44.c31 u32 flags, struct nvkm_fb_tile *tile) in nv44_fb_tile_init() argument
33 tile->addr = 0x00000001; /* mode = vram */ in nv44_fb_tile_init()
34 tile->addr |= addr; in nv44_fb_tile_init()
35 tile->limit = max(1u, addr + size) - 1; in nv44_fb_tile_init()
36 tile->pitch = pitch; in nv44_fb_tile_init()
40 nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv44_fb_tile_prog() argument
43 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv44_fb_tile_prog()
44 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv44_fb_tile_prog()
45 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv44_fb_tile_prog()
60 .tile.regions = 12,
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H A Dnv40.c31 struct nvkm_fb_tile *tile) in nv40_fb_tile_comp() argument
36 !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
38 tile->zcomp |= ((tile->tag->offset ) >> 8); in nv40_fb_tile_comp()
39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
56 .tile.regions = 8,
57 .tile.init = nv30_fb_tile_init,
58 .tile.comp = nv40_fb_tile_comp,
59 .tile.fini = nv20_fb_tile_fini,
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H A Dnv25.c31 struct nvkm_fb_tile *tile) in nv25_fb_tile_comp() argument
35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv25_fb_tile_comp()
36 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ in nv25_fb_tile_comp()
37 else tile->zcomp = 0x00200000; /* Z24S8 */ in nv25_fb_tile_comp()
38 tile->zcomp |= tile->tag->offset; in nv25_fb_tile_comp()
40 tile->zcomp |= 0x01000000; in nv25_fb_tile_comp()
48 .tile.regions = 8,
49 .tile.init = nv20_fb_tile_init,
50 .tile.comp = nv25_fb_tile_comp,
51 .tile.fini = nv20_fb_tile_fini,
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H A Dnv46.c31 u32 flags, struct nvkm_fb_tile *tile) in nv46_fb_tile_init() argument
34 if (!(flags & 4)) tile->addr = (0 << 3); in nv46_fb_tile_init()
35 else tile->addr = (1 << 3); in nv46_fb_tile_init()
37 tile->addr |= 0x00000001; /* mode = vram */ in nv46_fb_tile_init()
38 tile->addr |= addr; in nv46_fb_tile_init()
39 tile->limit = max(1u, addr + size) - 1; in nv46_fb_tile_init()
40 tile->pitch = pitch; in nv46_fb_tile_init()
46 .tile.regions = 15,
47 .tile.init = nv46_fb_tile_init,
48 .tile.fini = nv20_fb_tile_fini,
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H A Dnv41.c30 nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) in nv41_fb_tile_prog() argument
33 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv41_fb_tile_prog()
34 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv41_fb_tile_prog()
35 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv41_fb_tile_prog()
37 nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp); in nv41_fb_tile_prog()
50 .tile.regions = 12,
51 .tile.init = nv30_fb_tile_init,
52 .tile.comp = nv40_fb_tile_comp,
53 .tile.fini = nv20_fb_tile_fini,
54 .tile.prog = nv41_fb_tile_prog,
H A Dbase.c35 nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_fini() argument
37 fb->func->tile.fini(fb, region, tile); in nvkm_fb_tile_fini()
42 u32 pitch, u32 flags, struct nvkm_fb_tile *tile) in nvkm_fb_tile_init() argument
44 fb->func->tile.init(fb, region, addr, size, pitch, flags, tile); in nvkm_fb_tile_init()
48 nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) in nvkm_fb_tile_prog() argument
51 if (fb->func->tile.prog) { in nvkm_fb_tile_prog()
52 fb->func->tile.prog(fb, region, tile); in nvkm_fb_tile_prog()
201 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_init()
202 fb->func->tile.prog(fb, i, &fb->tile.region[i]); in nvkm_fb_init()
240 for (i = 0; i < fb->tile.regions; i++) in nvkm_fb_dtor()
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/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A Dcache.json67 …ounts the loads retired that get the data from the other core in the same tile in M state (Precise…
135 …data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. …
145 …ata forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. …
155 … data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
165 …r responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
175 …esponses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
185 … responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
195 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in E…
205 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in F…
215 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in M…
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv44.c31 nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) in nv44_gr_tile() argument
44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
56 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv44_gr_tile()
57 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv44_gr_tile()
58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
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/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_cr_defs_client.h64 * X1 MacroTile boundary, left tile X for second column of macrotiles (16MT mode) - 32 pixels across
65 * tile
70 * X2 MacroTile boundary, left tile X for third(16MT) column of macrotiles - 32 pixels across tile
75 * X3 MacroTile boundary, left tile X for fourth column of macrotiles (16MT) - 32 pixels across tile
85 * X1 MacroTile boundary, ltop tile Y for second column of macrotiles (16MT mode) - 32 pixels tile
91 * X2 MacroTile boundary, top tile Y for third(16MT) column of macrotiles - 32 pixels tile height
96 * X3 MacroTile boundary, top tile Y for fourth column of macrotiles (16MT) - 32 pixels tile height
110 * Maximum Y tile address visible on screen, 32 pixel tile height, 16Kx16K max screen size
115 * Maximum X tile address visible on screen, 32 pixel tile width, 16Kx16K max screen size
/linux/include/uapi/linux/media/raspberrypi/
H A Dpisp_be_config.h24 /* minimum allowed tile sizes anywhere in the pipeline */
310 * @offset_x: Horizontal offset into the LSC table of this tile
311 * @offset_y: Vertical offset into the LSC table of this tile
343 * @offset_x: Horizontal offset into the CAC table of this tile
344 * @offset_y: Horizontal offset into the CAC table of this tile
582 * @offset_x: Number of pixels cropped from the left of the tile
583 * @offset_y: Number of pixels cropped from the top of the tile
584 * @width: Width of the cropped tile output
585 * @height: Height of the cropped tile output
841 * enum pisp_tile_edge - PiSP Back End Tile positio
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/linux/drivers/hid/
H A Dhid-picolcd_fb.c22 * each. Each tile has 8x64 pixel, each data byte representing
23 * a 1-bit wide vertical line of the tile.
25 * The display can be updated at a tile granularity.
29 * | Tile 1 | Tile 1 | Tile 1 | Tile 1 |
31 * | Tile 2 | Tile 2 | Tile 2 | Tile 2 |
35 * | Tile 8 | Tile 8 | Tile 8 | Tile 8 |
89 /* Send a given tile to PicoLCD */
91 int chip, int tile) in picolcd_fb_send_tile() argument
114 hid_set_field(report1->field[0], 4, 0xb8 | tile); in picolcd_fb_send_tile()
127 tdata = vbitmap + (tile * 4 + chip) * 64; in picolcd_fb_send_tile()
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/linux/arch/arm/mach-versatile/
H A DKconfig129 bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 bool "Integrator/CTB36 (ARM1136JF-S) core tile"
178 the ARM926EJ-S core tile, while on an ARMv6/v7 kernel, at least
180 core tile options should be enabled.
183 bool "Support ARM1136J(F)-S Tile"
187 Enable support for the ARM1136 tile fitted to the
191 bool "Support ARM1176JZ(F)-S Tile"
194 Enable support for the ARM1176 tile fitted to the
198 bool "Support Multicore Cortex-A9 Tile"
201 Enable support for the Cortex-A9MPCore tile fitted to the
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/linux/drivers/media/platform/verisilicon/
H A Dhantro_hw.h144 * @tile_sizes: Tile sizes buffer
145 * @tile_filter: Tile vertical filter buffer
146 * @tile_sao: Tile SAO buffer
147 * @tile_bsd: Tile BSD control buffer
217 * @tile_edge: auxiliary DMA buffer for tile edge processing
219 * @misc: auxiliary DMA buffer for tile info, probabilities and hw counters
228 * @tile_info_offset: tile info offset into misc
229 * @tile_r_info: per-tile information array
230 * @tile_c_info: per-tile information array
231 * @last_tile_r: last number of tile rows
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/linux/drivers/gpu/drm/xe/tests/
H A Dxe_bo.c24 static int ccs_test_migrate(struct xe_tile *tile, struct xe_bo *bo, in ccs_test_migrate() argument
46 fence = xe_migrate_clear(tile->migrate, bo, bo->ttm.resource, in ccs_test_migrate()
109 offset = xe_device_ccs_bytes(tile_to_xe(tile), xe_bo_size(bo)); in ccs_test_migrate()
126 static void ccs_test_run_tile(struct xe_device *xe, struct xe_tile *tile, in ccs_test_run_tile() argument
134 unsigned int bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile); in ccs_test_run_tile()
138 kunit_info(test, "Testing vram id %u\n", tile->id); in ccs_test_run_tile()
152 ret = ccs_test_migrate(tile, bo, false, 0ULL, 0xdeadbeefdeadbeefULL, in ccs_test_run_tile()
158 ret = ccs_test_migrate(tile, bo, false, 0xdeadbeefdeadbeefULL, in ccs_test_run_tile()
164 ret = ccs_test_migrate(tile, bo, true, 0ULL, 0ULL, test, exec); in ccs_test_run_tile()
174 struct xe_tile *tile; in ccs_test_run_device() local
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