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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAMX.td31 def TILELOADD#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
36 def TILELOADDT1#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
42 (ins sibmem:$dst, TILE:$src),
56 def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins),
65 def PTILELOADDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
69 def PTILELOADDT1V : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
75 TILE:$src4), []>;
78 def PTILEZEROV : PseudoI<(outs TILE:$dst), (ins GR16:$src1, GR16:$src2),
79 [(set TILE:$dst, (int_x86_tilezero_internal
83 // Pseudo instructions, using immediates instead of tile registers.
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H A DX86FastTileConfig.cpp1 //===-- X86FastTileConfig.cpp - Fast Tile Register Configure---------------===//
12 /// know the shape of each physical tile registers, because the register
14 /// pass. It collects the shape information of each physical tile register
16 /// to tile config register.
55 return "Fast Tile Register Configure"; in getPassName()
79 "Fast Tile Register Configure", false, false)
81 "Fast Tile Register Configure", false, false)
86 // The instruction must have 3 operands: tile def, row, col. in isTileDef()
107 // PreTileConfig should configure the tile registers based on basic
115 // AMX instructions that define tile register. in configBasicBlock()
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H A DX86TileConfig.cpp1 //===-- X86TileConfig.cpp - Tile Register Configure----------------------===//
12 /// know the shape of each physical tile registers, because the register
14 /// pass. It collects the shape information of each physical tile register
16 /// to tile config register.
48 StringRef getPassName() const override { return "Tile Register Configure"; } in getPassName()
73 INITIALIZE_PASS_BEGIN(X86TileConfig, DEBUG_TYPE, "Tile Register Configure",
76 INITIALIZE_PASS_END(X86TileConfig, DEBUG_TYPE, "Tile Register Configure", false, in INITIALIZE_PASS_DEPENDENCY()
138 // Fill in the shape of each tile physical register. in INITIALIZE_PASS_DEPENDENCY()
147 // Here is the data format for the tile config. in INITIALIZE_PASS_DEPENDENCY()
151 // 16-17 tile0.colsb Tile 0 bytes per row. in INITIALIZE_PASS_DEPENDENCY()
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H A DX86LowerTileCopy.cpp1 //===-- X86LowerTileCopy.cpp - Expand Tile Copy Instructions---------------===//
9 // This file defines the pass which lower AMX tile copy instructions. Since
10 // there is no tile copy instruction, we need store tile register to stack
11 // and load from stack to another tile register. We need extra GR to hold
12 // the stride, and we need stack slot to hold the tile data register.
39 #define DEBUG_TYPE "x86-lower-tile-copy"
53 StringRef getPassName() const override { return "X86 Lower Tile Copy"; } in getPassName()
60 INITIALIZE_PASS_BEGIN(X86LowerTileCopy, "lowertilecopy", "Tile Copy Lowering",
62 INITIALIZE_PASS_END(X86LowerTileCopy, "lowertilecopy", "Tile Copy Lowering",
102 // Allocate stack slot for tile register in runOnMachineFunction()
H A DX86FastPreTileConfig.cpp1 //===-- X86FastPreTileConfig.cpp - Fast Tile Register Configure------------===//
9 /// \file Pass to preconfig the shape of physical tile registers
10 /// It inserts ldtilecfg ahead of each group of tile registers. The algorithm
11 /// walk each instruction of basic block in reverse order. All the tile
64 /// Has a bit set for tile virtual register for which it was determined
84 return "Fast Tile Register Preconfigure"; in getPassName()
87 /// Perform tile register configure.
98 "Fast Tile Register Preconfigure", false, false)
100 "Fast Tile Register Preconfigure", false, false)
149 // The use and def are in the same MBB. If the tile register is in mayLiveOut()
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H A DX86PreTileConfig.cpp1 //===-- X86PreTileConfig.cpp - Tile Register Pre-configure-----------------===//
45 #define DEBUG_TYPE "tile-pre-config"
51 ": Failed to config tile register, please define the shape earlier"); in emitErrorMsg()
178 return "Tile Register Pre-configure"; in getPassName()
206 "Tile Register Pre-configure", false, false)
209 "Tile Register Pre-configure", false, false) in INITIALIZE_PASS_DEPENDENCY()
265 // If there's call before the AMX, we need to reload tile config. in runOnMachineFunction()
268 else // Otherwise, we need tile config to live in this BB. in runOnMachineFunction()
306 // There's no AMX instruction if we didn't find a tile config live in point. in runOnMachineFunction()
315 // We are not able to config tile registers since the shape to config in runOnMachineFunction()
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H A DX86LowerAMXType.cpp164 // %117 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x in getShape()
271 Value *Tile = Bitcast->getOperand(0); in combineBitcastStore() local
272 auto *II = cast<IntrinsicInst>(Tile); in combineBitcastStore()
273 // Tile is output from AMX intrinsic. The first operand of the in combineBitcastStore()
282 std::array<Value *, 5> Args = {Row, Col, I8Ptr, Stride, Tile}; in combineBitcastStore()
471 assert(TileDef->getType()->isX86_AMXTy() && "Not define tile!"); in createTileStore()
473 assert(II && "Not tile intrinsic!"); in createTileStore()
490 assert(V->getType()->isX86_AMXTy() && "Not define tile!"); in replaceWithTileLoad()
492 // Get tile shape. in replaceWithTileLoad()
522 // Let all AMX tile data become volatile data, shorten the life range
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H A DX86.h88 /// Return a pass that config the tile registers.
91 /// Return a pass that preconfig the tile registers before fast reg allocation.
94 /// Return a pass that config the tile registers after fast reg allocation.
97 /// Return a pass that insert pseudo tile config instruction.
100 /// Return a pass that lower the tile copy instruction.
H A DX86PreAMXConfig.cpp
H A DX86LowerAMXIntrinsics.cpp78 Value *Ptr, Value *Stride, Value *Tile);
150 Value *Col, Value *Ptr, Value *Stride, Value *Tile) { in createTileLoadStoreLoops() argument
218 auto *BitCast = cast<BitCastInst>(Tile); in createTileLoadStoreLoops()
514 Value *M, *N, *Ptr, *Stride, *Tile; in lowerTileLoadStore() local
522 m_Value(Stride), m_Value(Tile))); in lowerTileLoadStore()
535 IsTileLoad ? nullptr : Tile); in lowerTileLoadStore()
/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Damxintrin.h20 __attribute__((__always_inline__, __nodebug__, __target__("amx-tile")))
28 /// Load tile configuration from a 64-byte memory location specified by
29 /// "mem_addr". The tile configuration includes the tile type palette, the
31 /// palette_id is zero, that signifies the init state for both the tile
32 /// config and the tile data, and the tiles are zeroed. Any invalid
46 /// Stores the current tile configuration to a 64-byte memory location
47 /// specified by "mem_addr". The tile configuration includes the tile type
62 /// Release the tile configuration to return to the init state, which
72 /// Load tile rows from memory specifieid by "base" address and "stride" into
73 /// destination tile "dst" using the tile configuration previously configured
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H A Damxcomplexintrin.h22 /// accumulate the results into a packed single precision tile. Each dword
58 /// The destination tile. Max size is 1024 Bytes.
60 /// The 1st source tile. Max size is 1024 Bytes.
62 /// The 2nd source tile. Max size is 1024 Bytes.
66 /// accumulate the results into a packed single precision tile. Each dword
103 /// The destination tile. Max size is 1024 Bytes.
105 /// The 1st source tile. Max size is 1024 Bytes.
107 /// The 2nd source tile. Max size is 1024 Bytes.
123 /// accumulate the results into a packed single precision tile. Each dword
133 /// The destination tile. Max size is 1024 Bytes.
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H A Damxfp16intrin.h21 /// result back to tile \a dst.
49 /// The destination tile. Max size is 1024 Bytes.
51 /// The 1st source tile. Max size is 1024 Bytes.
53 /// The 2nd source tile. Max size is 1024 Bytes.
/freebsd/lib/libpmc/pmu-events/arch/x86/knightslanding/
H A Dcache.json60 …ion": "Counts the loads retired that get the data from the other core in the same tile in M state",
126 …data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. …
137 …ata forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. …
148 … data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.",
159 …or reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state",
170 …esponses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.",
181 … responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.",
192 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in E…
203 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in F…
214 …refetch code read requests that accounts for responses which hit its own tile's L2 with data in M…
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H A Dmemory.json55 …ch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
121 …ch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
176 … any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
242 …unts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
308 …": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
374 …e data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
440 …nd split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
506 …nd prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
572 …L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
638 … cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Darm,vexpress-juno.yaml22 The motherboard and each core tile should be described by a separate Device
23 Tree source file, with the tile's description including the motherboard file
33 The root node indicates the CPU SoC on the core tile, and this
35 string shall match the name given in the core tile's technical reference
37 further subvariants are released of the core tile, even more fine-granular
46 in MPCore configuration in a test chip on the core tile. See ARM
52 in a test chip on the core tile. It is intended to evaluate NEON, FPU
58 cores in a MPCore configuration in a test chip on the core tile. See
64 A15 CPU cores in a test chip on the core tile. This is the first test
72 in a test chip on the core tile
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H A Dvexpress-scc.txt16 where <model> is the full tile model name (as used
17 in the tile's Technical Reference Manual),
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Darm-realview-eb.dts34 * This is the core tile with the CPU and GIC etc for the
40 * Unless specified, QEMU will emulate an ARM926EJ-S core tile.
64 * to the GIC on the core tile.
H A Darm-realview-eb-11mp-bbrevd-ctrevb.dts28 * the Rev B core tile.
31 model = "ARM RealView Emulation Baseboard Rev D with ARM11MPCore Core Tile Rev B";
H A Darm-realview-eb-11mp.dts27 model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C Core Tile";
31 * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB.
H A Darm-realview-eb-mp.dtsi119 * to the GIC on the core tile.
180 * routed to the core tile, but they can be reached on the secondary
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dnxp,dw100.yaml15 and wide angle lenses. It is implemented with a line/tile-cache based
16 architecture. With configurable address mapping look up tables and per tile
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTileShapeInfo.h10 /// AMX hardware requires to config the shape of tile data register before use.
14 /// tile config and register allocator. The row and column are machine operand
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DOpenACCKinds.h281 /// 'tile' clause, allowed on 'loop' and Combined constructs.
282 Tile, enumerator
437 case OpenACCClauseKind::Tile: in printOpenACCClauseKind()
438 return Out << "tile"; in printOpenACCClauseKind()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DSMEInstrFormats.td61 : Pseudo<(outs), (ins i32imm:$tile, PPR3bAny:$pn, PPR3bAny:$pm,
102 …Pseudo<(outs), (ins tile_imm:$tile, MatrixIndexGPR32Op12_15:$Rs, imm_ty:$imm, multi_vector_ty:$Zn)…
116 … Pseudo<(outs vector_ty:$Zn), (ins tile_imm:$tile, MatrixIndexGPR32Op12_15:$Rs, imm_ty:$imm), []> {
207 …: Pat<(intrinsic tile_imm:$tile, (i32 (tileslice MatrixIndexGPR32Op12_15:$base, index_ty:$offset))…
208 …(!cast<Instruction>(name # _PSEUDO) $tile, $base, $offset, (REG_SEQUENCE ZPR2Mul2, vt:$Zn1, zsub0,…
211 …: Pat<(intrinsic tile_imm:$tile, (i32 (tileslice MatrixIndexGPR32Op12_15:$base, index_ty:$offset))…
212 …(!cast<Instruction>(name # _PSEUDO) $tile, $base, $offset, (REG_SEQUENCE ZPR4Mul4, vt:$Zn1, zsub0,…
219 …: Pat<(out_vt (intrinsic tile_imm:$tile, (i32 (tileslice MatrixIndexGPR32Op12_15:$base, index_ty:$…
220 (!cast<Instruction>(name # _PSEUDO) $tile, $base, $offset)>;
227 : Pat<(intrinsic imm_ty:$tile, (pg_ty PPR3bAny:$Pn), (pg_ty PPR3bAny:$Pm), vt:$Zn, vt:$Zm),
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