xref: /linux/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml (revision a9e6060bb2a6cae6d43a98ec0794844ad01273d3) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Audio Graph based Tegra sound card driver
8
9description: |
10  This is based on generic audio graph card driver along with additional
11  customizations for Tegra platforms. It uses the same bindings with
12  additional standard clock DT bindings required for Tegra.
13
14maintainers:
15  - Jon Hunter <jonathanh@nvidia.com>
16  - Sameer Pujar <spujar@nvidia.com>
17
18allOf:
19  - $ref: audio-graph.yaml#
20
21properties:
22  compatible:
23    enum:
24      - nvidia,tegra210-audio-graph-card
25      - nvidia,tegra186-audio-graph-card
26      - nvidia,tegra264-audio-graph-card
27
28  clocks:
29    minItems: 2
30
31  clock-names:
32    items:
33      - const: pll_a
34      - const: plla_out0
35
36  assigned-clocks:
37    minItems: 1
38    maxItems: 3
39
40  assigned-clock-parents:
41    minItems: 1
42    maxItems: 3
43
44  assigned-clock-rates:
45    minItems: 1
46    maxItems: 3
47
48  interconnects:
49    items:
50      - description: APE read memory client
51      - description: APE write memory client
52
53  interconnect-names:
54    items:
55      - const: dma-mem # read
56      - const: write
57
58  iommus:
59    maxItems: 1
60
61required:
62  - clocks
63  - clock-names
64  - assigned-clocks
65  - assigned-clock-parents
66
67unevaluatedProperties: false
68
69examples:
70  - |
71    #include<dt-bindings/clock/tegra210-car.h>
72
73    tegra_sound {
74        compatible = "nvidia,tegra210-audio-graph-card";
75
76        clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
77                 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
78        clock-names = "pll_a", "plla_out0";
79
80        assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
81                          <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
82                          <&tegra_car TEGRA210_CLK_EXTERN1>;
83        assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
84        assigned-clock-rates = <368640000>, <49152000>, <12288000>;
85
86        dais = /* FE */
87               <&admaif1_port>,
88               /* Router */
89               <&xbar_i2s1_port>,
90               /* I/O DAP Ports */
91               <&i2s1_port>;
92
93        label = "jetson-tx1-ape";
94    };
95
96    // The ports are defined for AHUB and its child devices.
97    ahub@702d0800 {
98        compatible = "nvidia,tegra210-ahub";
99        reg = <0x702d0800 0x800>;
100        clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
101        clock-names = "ahub";
102        assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
103        assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
104        #address-cells = <1>;
105        #size-cells = <1>;
106        ranges = <0x702d0000 0x702d0000 0x0000e400>;
107
108        ports {
109            #address-cells = <1>;
110            #size-cells = <0>;
111
112            port@0 {
113                reg = <0x0>;
114                xbar_admaif1_ep: endpoint {
115                    remote-endpoint = <&admaif1_ep>;
116                };
117            };
118
119            // ...
120
121            xbar_i2s1_port: port@a {
122                reg = <0xa>;
123                xbar_i2s1_ep: endpoint {
124                    remote-endpoint = <&i2s1_cif_ep>;
125                };
126            };
127        };
128
129        admaif@702d0000 {
130            compatible = "nvidia,tegra210-admaif";
131            reg = <0x702d0000 0x800>;
132            dmas = <&adma 1>,  <&adma 1>,
133                   <&adma 2>,  <&adma 2>,
134                   <&adma 3>,  <&adma 3>,
135                   <&adma 4>,  <&adma 4>,
136                   <&adma 5>,  <&adma 5>,
137                   <&adma 6>,  <&adma 6>,
138                   <&adma 7>,  <&adma 7>,
139                   <&adma 8>,  <&adma 8>,
140                   <&adma 9>,  <&adma 9>,
141                   <&adma 10>, <&adma 10>;
142            dma-names = "rx1",  "tx1",
143                        "rx2",  "tx2",
144                        "rx3",  "tx3",
145                        "rx4",  "tx4",
146                        "rx5",  "tx5",
147                        "rx6",  "tx6",
148                        "rx7",  "tx7",
149                        "rx8",  "tx8",
150                        "rx9",  "tx9",
151                        "rx10", "tx10";
152
153            ports {
154                #address-cells = <1>;
155                #size-cells = <0>;
156
157                admaif1_port: port@0 {
158                    reg = <0x0>;
159                    admaif1_ep: endpoint {
160                        remote-endpoint = <&xbar_admaif1_ep>;
161                    };
162                };
163
164                // More ADMAIF ports to follow
165            };
166        };
167
168        i2s@702d1000 {
169            compatible = "nvidia,tegra210-i2s";
170            clocks = <&tegra_car TEGRA210_CLK_I2S0>;
171            clock-names = "i2s";
172            assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
173            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
174            assigned-clock-rates = <1536000>;
175            reg = <0x702d1000 0x100>;
176
177            ports {
178                #address-cells = <1>;
179                #size-cells = <0>;
180
181                port@0 {
182                    reg = <0x0>;
183
184                    i2s1_cif_ep: endpoint {
185                        remote-endpoint = <&xbar_i2s1_ep>;
186                    };
187                };
188
189                i2s1_port: port@1 {
190                    reg = <0x1>;
191
192                    i2s1_dap: endpoint {
193                        dai-format = "i2s";
194                    };
195                };
196            };
197        };
198    };
199
200...
201