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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124.dtsi49 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
50 <&tegra_car TEGRA124_CLK_AFI>,
51 <&tegra_car TEGRA124_CLK_PLL_E>,
52 <&tegra_car TEGRA124_CLK_CML0>;
54 resets = <&tegra_car 70>,
55 <&tegra_car 72>,
56 <&tegra_car 74>;
95 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
97 resets = <&tegra_car 28>, <&mc TEGRA124_MC_RESET_HC>;
110 clocks = <&tegra_car TEGRA124_CLK_VI>;
[all …]
H A Dtegra20-plutux.dts57 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
58 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
59 <&tegra_car TEGRA20_CLK_CDEV1>;
H A Dtegra20-tec.dts66 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
67 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
68 <&tegra_car TEGRA20_CLK_CDEV1>;
H A Dtegra20-medcom-wide.dts92 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
93 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
94 <&tegra_car TEGRA20_CLK_CDEV1>;
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi44 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
45 <&tegra_car TEGRA124_CLK_AFI>,
46 <&tegra_car TEGRA124_CLK_PLL_E>,
47 <&tegra_car TEGRA124_CLK_CML0>;
49 resets = <&tegra_car 70>,
50 <&tegra_car 72>,
51 <&tegra_car 74>;
91 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
93 resets = <&tegra_car 28>;
107 clocks = <&tegra_car TEGRA124_CLK_DISP1>;
[all …]
/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-host1x.yaml255 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
257 resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
269 clocks = <&tegra_car TEGRA20_CLK_MPE>;
270 resets = <&tegra_car 60>;
278 clocks = <&tegra_car TEGRA20_CLK_VI>;
279 resets = <&tegra_car 100>;
287 clocks = <&tegra_car TEGRA20_CLK_EPP>;
288 resets = <&tegra_car 19>;
296 clocks = <&tegra_car TEGRA20_CLK_ISP>;
297 resets = <&tegra_car 23>;
[all …]
H A Dnvidia,tegra124-sor.yaml177 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
178 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
179 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
180 <&tegra_car TEGRA210_CLK_PLL_DP>,
181 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
183 resets = <&tegra_car 182>;
H A Dnvidia,tegra124-dpaux.yaml125 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
126 <&tegra_car TEGRA210_CLK_PLL_DP>;
128 resets = <&tegra_car 181>;
/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra30-ahub.txt71 clocks = <&tegra_car 106>, <&tegra_car 107>;
73 resets = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
74 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
75 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
76 <&tegra_car 110>, <&tegra_car 10>;
H A Dnvidia,tegra-audio-graph-card.yaml77 clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
78 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
81 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
82 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
83 <&tegra_car TEGRA210_CLK_EXTERN1>;
84 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
101 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
103 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
104 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
171 clocks = <&tegra_car TEGRA210_CLK_I2S0>;
[all …]
H A Dnvidia,tegra210-ahub.yaml138 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
140 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
141 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
175 clocks = <&tegra_car TEGRA210_CLK_I2S0>;
177 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
178 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
186 clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
188 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
189 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
H A Dnvidia,tegra30-hda.yaml187 clocks = <&tegra_car TEGRA124_CLK_HDA>,
188 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
189 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
191 resets = <&tegra_car 125>, /* hda */
192 <&tegra_car 128>, /* hda2hdmi */
193 <&tegra_car 111>; /* hda2codec_2x */
H A Dnvidia,tegra-audio-trimslice.yaml31 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
H A Dnvidia,tegra-audio-sgtl5000.yaml63 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
64 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
65 <&tegra_car TEGRA30_CLK_EXTERN1>;
H A Dnvidia,tegra-audio-max98090.yaml93 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
94 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
95 <&tegra_car TEGRA124_CLK_EXTERN1>;
H A Dnvidia,tegra210-dmic.yaml92 clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
94 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
95 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
H A Dnvidia,tegra210-i2s.yaml109 clocks = <&tegra_car TEGRA210_CLK_I2S0>;
111 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
112 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra124-xusb.yaml169 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
170 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
171 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
172 <&tegra_car TEGRA124_CLK_XUSB_SS>,
173 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
174 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
175 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
176 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
177 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
178 <&tegra_car TEGRA124_CLK_CLK_M>,
[all …]
H A Dnvidia,tegra-xudc.yaml194 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>,
195 <&tegra_car TEGRA210_CLK_XUSB_SS>,
196 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>,
197 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
198 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>;
/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt193 clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
195 resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
295 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
296 <&tegra_car TEGRA30_CLK_AFI>,
297 <&tegra_car TEGRA30_CLK_PLL_E>,
298 <&tegra_car TEGRA30_CLK_CML0>;
300 resets = <&tegra_car 70>,
301 <&tegra_car 72>,
302 <&tegra_car 74>;
399 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dnvidia,tegra20-sdhci.yaml274 clocks = <&tegra_car 14>;
275 resets = <&tegra_car 14>;
291 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
292 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
294 resets = <&tegra_car 14>;
308 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
309 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
310 <&tegra_car TEGRA210_CLK_PLL_C4>;
311 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
/linux/Documentation/devicetree/bindings/ata/
H A Dnvidia,tegra-ahci.yaml168 clocks = <&tegra_car TEGRA210_CLK_SATA>,
169 <&tegra_car TEGRA210_CLK_SATA_OOB>;
171 resets = <&tegra_car 124>,
172 <&tegra_car 129>,
173 <&tegra_car 123>;
/linux/Documentation/devicetree/bindings/cpufreq/
H A Dnvidia,tegra124-cpufreq.txt31 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
32 <&tegra_car TEGRA124_CLK_PLL_X>,
33 <&tegra_car TEGRA124_CLK_PLL_P>,
/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,nvec.yaml79 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
80 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
82 resets = <&tegra_car 67>;
/linux/Documentation/devicetree/bindings/bus/
H A Dnvidia,tegra20-gmi.txt81 clocks = <&tegra_car TEGRA20_CLK_NOR>;
83 resets = <&tegra_car 42>;
116 clocks = <&tegra_car TEGRA20_CLK_NOR>;
118 resets = <&tegra_car 42>;

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