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Searched +full:tegra210 +full:- +full:timer (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/rtc/
H A Dnvidia,tegra20-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra real-time clock
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 from low-power state.
21 - const: nvidia,tegra20-rtc
22 - items:
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/linux/drivers/memory/tegra/
H A Dtegra210-emc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
21 #include "tegra210-emc.h"
22 #include "tegra210-mc.h"
62 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
69 next->trim_perch_regs[EMC ## chan ## \
559 static void tegra210_emc_train(struct timer_list *timer) in tegra210_emc_train() argument
561 struct tegra210_emc *emc = timer_container_of(emc, timer, training); in tegra210_emc_train()
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
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/linux/drivers/clk/tegra/
H A Dclk-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/tegra210-car.h>
18 #include <dt-bindings/reset/tegra210-car.h>
23 #include "clk-id.h"
27 * banks present in the Tegra210 CAR IP block. The banks are
264 * SDM fractional divisor is 16-bit 2's complement signed number within
265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
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H A Dclk-tegra-periph.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-id.h"
130 #define MASK(x) (BIT(x) - 1)
774 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
787 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
873 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in periph_clk_init()
877 bank = get_reg_bank(data->periph.gate.clk_num); in periph_clk_init()
881 data->periph.gate.regs = bank; in periph_clk_init()
899 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in gate_clk_init()
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/linux/drivers/usb/gadget/udc/
H A Dtegra-xudc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/dma-mapping.h>
246 return (le32_to_cpu(ctx->member) >> (shift)) & (mask); \
253 tmp = le32_to_cpu(ctx->member) & ~((mask) << (shift)); \
255 ctx->member = cpu_to_le32(tmp); \
338 return (le32_to_cpu(trb->member) >> (shift)) & (mask); \
345 tmp = le32_to_cpu(trb->member) & ~((mask) << (shift)); \
347 trb->member = cpu_to_le32(tmp); \
563 return readl(xudc->fpci + offset); in fpci_readl()
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/linux/drivers/gpu/drm/tegra/
H A Ddc.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
44 stats->frames = 0; in tegra_dc_stats_reset()
45 stats->vblank = 0; in tegra_dc_stats_reset()
46 stats->underflow = 0; in tegra_dc_stats_reset()
47 stats->overflow = 0; in tegra_dc_stats_reset()
66 offset = 0x000 + (offset - 0x500); in tegra_plane_offset()
67 return plane->offset + offset; in tegra_plane_offset()
71 offset = 0x180 + (offset - 0x700); in tegra_plane_offset()
72 return plane->offset + offset; in tegra_plane_offset()
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/linux/
H A DMAINTAINERS5 ----------
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