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Searched +full:tegra210 +full:- +full:admaif (Results 1 – 15 of 15) sorted by relevance

/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra210-admaif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra210 ADMAIF
10 ADMAIF is the interface between ADMA and AHUB. Each ADMA channel
12 ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF
14 ADMAIF Rx channel.
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
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H A Dnvidia,tegra210-ahub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra210 AHUB
11 for audio pre-processing, post-processing and a programmable full
14 engine through ADMAIF.
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^ahub@[0-9a-f]*$"
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H A Dnvidia,tegra-audio-graph-card.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Sameer Pujar <spujar@nvidia.com>
19 - $ref: audio-graph.yaml#
24 - nvidia,tegra210-audio-graph-card
25 - nvidia,tegra186-audio-graph-card
26 - nvidia,tegra264-audio-graph-card
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/linux/sound/soc/tegra/
H A Dtegra210_admaif.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES.
5 // tegra210_admaif.c - Tegra ADMAIF driver
24 #define CH_TX_REG(reg, id) CH_REG(admaif->soc_data->tx_base, reg, id)
26 #define CH_RX_REG(reg, id) CH_REG(admaif->soc_data->rx_base, reg, id)
37 REG_DEFAULTS((id) - 1, \
70 ADMAIF_REG_DEFAULTS(1, TEGRA210),
71 ADMAIF_REG_DEFAULTS(2, TEGRA210),
72 ADMAIF_REG_DEFAULTS(3, TEGRA210),
73 ADMAIF_REG_DEFAULTS(4, TEGRA210),
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
5 tristate "SoC Audio for the Tegra System-on-Chip"
63 tristate "Tegra210 AHUB module"
69 Say Y or M if you want to add support for Tegra210 AHUB module.
72 tristate "Tegra210 DMIC module"
79 Say Y or M if you want to add support for Tegra210 DMIC module.
82 tristate "Tegra210 I2S module"
85 Config to enable the Inter-IC Sound (I2S) Controller which
86 implements full-duplex and bidirectional and single direction
87 point-to-point serial interfaces. It can interface with I2S
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H A Dtegra210_admaif.h1 /* SPDX-License-Identifier: GPL-2.0-only
2 * SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES.
5 * tegra210_admaif.h - Tegra ADMAIF registers
13 /* Tegra210 specific */
77 /* Default values - Tegra210 */
99 /* Default values - Tegra186 */
141 /* Default values - Tegra264 */
H A Dtegra210_ahub.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra210_ahub.c - Tegra210 AHUB driver
5 // Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
22 struct soc_enum *e = (struct soc_enum *)kctl->private_value; in tegra_ahub_get_value_enum()
29 for (i = 0; i < ahub->soc_data->reg_count; i++) { in tegra_ahub_get_value_enum()
32 reg = e->reg + (ahub->soc_data->xbar_part_size * i); in tegra_ahub_get_value_enum()
34 reg_val &= ahub->soc_data->mask[i]; in tegra_ahub_get_value_enum()
38 (8 * cmpnt->val_bytes * i); in tegra_ahub_get_value_enum()
44 for (i = 0; i < e->items; i++) { in tegra_ahub_get_value_enum()
45 if (bit_pos == e->values[i]) { in tegra_ahub_get_value_enum()
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H A Dtegra210_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES.
5 // tegra210_i2s.c - Tegra210 I2S driver
32 * On Tegra210, I2S4 has "i2s4a" and "i2s4b" pins and below update
56 regmap_write(i2s->regmap, TEGRA210_I2S_SLOT_CTRL + i2s->soc_data->i2s_ctrl_offset, in tegra210_i2s_set_slot_ctrl()
57 total_slots - 1); in tegra210_i2s_set_slot_ctrl()
58 regmap_write(i2s->regmap, TEGRA210_I2S_TX_SLOT_CTRL + i2s->soc_data->tx_offset, in tegra210_i2s_set_slot_ctrl()
60 regmap_write(i2s->regmap, TEGRA210_I2S_RX_SLOT_CTRL, rx_slot_mask); in tegra210_i2s_set_slot_ctrl()
70 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL + i2s->soc_data->i2s_ctrl_offset, &val); in tegra210_i2s_set_clock_rate()
76 err = clk_set_rate(i2s->clk_i2s, clock_rate); in tegra210_i2s_set_clock_rate()
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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H A Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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H A Dtegra210-p2371-2180.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra210-p2180.dtsi"
5 #include "tegra210-p2597.dtsi"
9 compatible = "nvidia,p2371-2180", "nvidia,tegra210";
14 hvddio-pex-supply = <&vdd_1v8>;
15 dvddio-pex-supply = <&vdd_pex_1v05>;
16 vddio-pex-ctl-supply = <&vdd_1v8>;
19 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
20 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
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H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
[all …]
H A Dtegra210-p3450-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h>
8 #include "tegra210.dtsi"
12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
22 stdout-path = "serial0:115200n8";
33 hvddio-pex-supply = <&vdd_1v8>;
34 dvddio-pex-supply = <&vdd_pex_1v05>;
[all …]
/linux/drivers/dma/
H A Dtegra210-adma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ADMA driver for Nvidia's Tegra210 ADMA controller.
18 #include "virt-dma.h"
84 * struct tegra_adma_chip_data - Tegra chip specific data
134 * struct tegra_adma_chan_regs - Tegra ADMA channel registers
148 * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests.
159 * struct tegra_adma_chan - Tegra ADMA channel information
184 * struct tegra_adma - Tegra ADMA controller information
209 writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg); in tdma_write()
214 return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg); in tdma_read()
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