Lines Matching +full:tegra210 +full:- +full:admaif
1 // SPDX-License-Identifier: GPL-2.0-only
3 * ADMA driver for Nvidia's Tegra210 ADMA controller.
18 #include "virt-dma.h"
84 * struct tegra_adma_chip_data - Tegra chip specific data
134 * struct tegra_adma_chan_regs - Tegra ADMA channel registers
148 * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests.
159 * struct tegra_adma_chan - Tegra ADMA channel information
184 * struct tegra_adma - Tegra ADMA controller information
209 writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg); in tdma_write()
214 return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg); in tdma_read()
219 writel(val, tdma->ch_base_addr + tdma->cdata->global_reg_offset + reg); in tdma_ch_global_write()
224 writel(val, tdc->chan_addr + reg); in tdma_ch_write()
229 return readl(tdc->chan_addr + reg); in tdma_ch_read()
245 return tdc->tdma->dev; in tdc2dev()
258 memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig)); in tegra_adma_slave_config()
272 tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_CHGRP + (tdma->ch_page_no * 0x4), 0xff); in tegra186_adma_global_page_config()
273 tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_RX_REQ + (tdma->ch_page_no * 0x4), 0x1ffffff); in tegra186_adma_global_page_config()
274 tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ + (tdma->ch_page_no * 0x4), 0xffffff); in tegra186_adma_global_page_config()
279 u32 global_page_offset = tdma->ch_page_no * TEGRA264_ADMA_GLOBAL_PAGE_OFFSET; in tegra264_adma_global_page_config()
282 if (tdma->ch_page_no) { in tegra264_adma_global_page_config()
306 tdma_ch_global_write(tdma, tdma->cdata->global_int_clear, 0x1); in tegra_adma_init()
308 if (!tdma->base_addr) in tegra_adma_init()
316 tdma->base_addr + in tegra_adma_init()
317 tdma->cdata->global_reg_offset + in tegra_adma_init()
323 if (tdma->cdata->set_global_pg_config) in tegra_adma_init()
324 tdma->cdata->set_global_pg_config(tdma); in tegra_adma_init()
335 struct tegra_adma *tdma = tdc->tdma; in tegra_adma_request_alloc()
336 unsigned int sreq_index = tdc->sreq_index; in tegra_adma_request_alloc()
338 if (tdc->sreq_reserved) in tegra_adma_request_alloc()
339 return tdc->sreq_dir == direction ? 0 : -EINVAL; in tegra_adma_request_alloc()
341 if (sreq_index > tdma->cdata->ch_req_max) { in tegra_adma_request_alloc()
342 dev_err(tdma->dev, "invalid DMA request\n"); in tegra_adma_request_alloc()
343 return -EINVAL; in tegra_adma_request_alloc()
348 if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) { in tegra_adma_request_alloc()
349 dev_err(tdma->dev, "DMA request reserved\n"); in tegra_adma_request_alloc()
350 return -EINVAL; in tegra_adma_request_alloc()
355 if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) { in tegra_adma_request_alloc()
356 dev_err(tdma->dev, "DMA request reserved\n"); in tegra_adma_request_alloc()
357 return -EINVAL; in tegra_adma_request_alloc()
362 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", in tegra_adma_request_alloc()
363 dma_chan_name(&tdc->vc.chan)); in tegra_adma_request_alloc()
364 return -EINVAL; in tegra_adma_request_alloc()
367 tdc->sreq_dir = direction; in tegra_adma_request_alloc()
368 tdc->sreq_reserved = true; in tegra_adma_request_alloc()
375 struct tegra_adma *tdma = tdc->tdma; in tegra_adma_request_free()
377 if (!tdc->sreq_reserved) in tegra_adma_request_free()
380 switch (tdc->sreq_dir) { in tegra_adma_request_free()
382 clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved); in tegra_adma_request_free()
386 clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved); in tegra_adma_request_free()
390 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", in tegra_adma_request_free()
391 dma_chan_name(&tdc->vc.chan)); in tegra_adma_request_free()
395 tdc->sreq_reserved = false; in tegra_adma_request_free()
425 if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS, in tegra_adma_stop()
432 kfree(tdc->desc); in tegra_adma_stop()
433 tdc->desc = NULL; in tegra_adma_stop()
438 struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc); in tegra_adma_start()
445 list_del(&vd->node); in tegra_adma_start()
447 desc = to_tegra_adma_desc(&vd->tx); in tegra_adma_start()
454 ch_regs = &desc->ch_regs; in tegra_adma_start()
456 tdc->tx_buf_pos = 0; in tegra_adma_start()
457 tdc->tx_buf_count = 0; in tegra_adma_start()
458 tdma_ch_write(tdc, ADMA_CH_TC - tdc->tdma->cdata->ch_tc_offset_diff, ch_regs->tc); in tegra_adma_start()
459 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); in tegra_adma_start()
460 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR - tdc->tdma->cdata->ch_tc_offset_diff, in tegra_adma_start()
461 ch_regs->src_addr); in tegra_adma_start()
462 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR - tdc->tdma->cdata->ch_tc_offset_diff, in tegra_adma_start()
463 ch_regs->trg_addr); in tegra_adma_start()
465 if (!tdc->tdma->cdata->global_ch_fifo_base) in tegra_adma_start()
466 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl); in tegra_adma_start()
467 else if (tdc->global_ch_fifo_offset) in tegra_adma_start()
468 tdma_write(tdc->tdma, tdc->global_ch_fifo_offset, ch_regs->fifo_ctrl); in tegra_adma_start()
470 if (tdc->global_ch_config_offset) in tegra_adma_start()
471 tdma_write(tdc->tdma, tdc->global_ch_config_offset, ch_regs->global_config); in tegra_adma_start()
473 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config); in tegra_adma_start()
478 tdc->desc = desc; in tegra_adma_start()
483 struct tegra_adma_desc *desc = tdc->desc; in tegra_adma_get_residue()
485 unsigned int pos = tdma_ch_read(tdc, ADMA_CH_XFER_STATUS - in tegra_adma_get_residue()
486 tdc->tdma->cdata->ch_tc_offset_diff); in tegra_adma_get_residue()
492 if (pos < tdc->tx_buf_pos) in tegra_adma_get_residue()
493 tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos); in tegra_adma_get_residue()
495 tdc->tx_buf_count += pos - tdc->tx_buf_pos; in tegra_adma_get_residue()
497 periods_remaining = tdc->tx_buf_count % desc->num_periods; in tegra_adma_get_residue()
498 tdc->tx_buf_pos = pos; in tegra_adma_get_residue()
500 return desc->buf_len - (periods_remaining * desc->period_len); in tegra_adma_get_residue()
508 spin_lock(&tdc->vc.lock); in tegra_adma_isr()
511 if (status == 0 || !tdc->desc) { in tegra_adma_isr()
512 spin_unlock(&tdc->vc.lock); in tegra_adma_isr()
516 vchan_cyclic_callback(&tdc->desc->vd); in tegra_adma_isr()
518 spin_unlock(&tdc->vc.lock); in tegra_adma_isr()
528 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_issue_pending()
530 if (vchan_issue_pending(&tdc->vc)) { in tegra_adma_issue_pending()
531 if (!tdc->desc) in tegra_adma_issue_pending()
535 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_issue_pending()
551 struct tegra_adma_desc *desc = tdc->desc; in tegra_adma_pause()
552 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; in tegra_adma_pause()
555 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); in tegra_adma_pause()
556 ch_regs->ctrl |= (1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT); in tegra_adma_pause()
557 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); in tegra_adma_pause()
559 while (dcnt-- && !tegra_adma_is_paused(tdc)) in tegra_adma_pause()
564 return -EBUSY; in tegra_adma_pause()
573 struct tegra_adma_desc *desc = tdc->desc; in tegra_adma_resume()
574 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; in tegra_adma_resume()
576 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); in tegra_adma_resume()
577 ch_regs->ctrl &= ~(1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT); in tegra_adma_resume()
578 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); in tegra_adma_resume()
589 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_terminate_all()
591 if (tdc->desc) in tegra_adma_terminate_all()
595 vchan_get_all_descriptors(&tdc->vc, &head); in tegra_adma_terminate_all()
596 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_terminate_all()
597 vchan_dma_desc_free_list(&tdc->vc, &head); in tegra_adma_terminate_all()
617 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_tx_status()
619 vd = vchan_find_desc(&tdc->vc, cookie); in tegra_adma_tx_status()
621 desc = to_tegra_adma_desc(&vd->tx); in tegra_adma_tx_status()
622 residual = desc->ch_regs.tc; in tegra_adma_tx_status()
623 } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) { in tegra_adma_tx_status()
629 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_tx_status()
649 return (burst_size - 1) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT; in tegra186_adma_get_burst_config()
657 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; in tegra_adma_set_xfer_params()
658 const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata; in tegra_adma_set_xfer_params()
661 if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS) in tegra_adma_set_xfer_params()
662 return -EINVAL; in tegra_adma_set_xfer_params()
668 burst_size = tdc->sconfig.dst_maxburst; in tegra_adma_set_xfer_params()
669 ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1); in tegra_adma_set_xfer_params()
670 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index, in tegra_adma_set_xfer_params()
671 cdata->ch_req_mask, in tegra_adma_set_xfer_params()
672 cdata->ch_req_tx_shift); in tegra_adma_set_xfer_params()
673 ch_regs->src_addr = buf_addr; in tegra_adma_set_xfer_params()
679 burst_size = tdc->sconfig.src_maxburst; in tegra_adma_set_xfer_params()
680 ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1); in tegra_adma_set_xfer_params()
681 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index, in tegra_adma_set_xfer_params()
682 cdata->ch_req_mask, in tegra_adma_set_xfer_params()
683 cdata->ch_req_rx_shift); in tegra_adma_set_xfer_params()
684 ch_regs->trg_addr = buf_addr; in tegra_adma_set_xfer_params()
689 return -EINVAL; in tegra_adma_set_xfer_params()
692 ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir, cdata->ch_dir_mask, in tegra_adma_set_xfer_params()
693 cdata->ch_dir_shift) | in tegra_adma_set_xfer_params()
694 ADMA_CH_CTRL_MODE_CONTINUOUS(cdata->ch_mode_shift) | in tegra_adma_set_xfer_params()
696 ch_regs->config |= cdata->adma_get_burst_config(burst_size); in tegra_adma_set_xfer_params()
698 if (cdata->global_ch_config_base) in tegra_adma_set_xfer_params()
699 ch_regs->global_config |= cdata->ch_config; in tegra_adma_set_xfer_params()
701 ch_regs->config |= cdata->ch_config; in tegra_adma_set_xfer_params()
704 * 'sreq_index' represents the current ADMAIF channel number and as per in tegra_adma_set_xfer_params()
708 * ADMA FIFO size is set as per below (based on default ADMAIF channel in tegra_adma_set_xfer_params()
714 if (tdc->sreq_index > cdata->sreq_index_offset) in tegra_adma_set_xfer_params()
715 ch_regs->fifo_ctrl = in tegra_adma_set_xfer_params()
716 ADMA_CH_REG_FIELD_VAL(2, cdata->ch_fifo_size_mask, in tegra_adma_set_xfer_params()
719 ch_regs->fifo_ctrl = in tegra_adma_set_xfer_params()
720 ADMA_CH_REG_FIELD_VAL(3, cdata->ch_fifo_size_mask, in tegra_adma_set_xfer_params()
723 ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK; in tegra_adma_set_xfer_params()
755 desc->buf_len = buf_len; in tegra_adma_prep_dma_cyclic()
756 desc->period_len = period_len; in tegra_adma_prep_dma_cyclic()
757 desc->num_periods = buf_len / period_len; in tegra_adma_prep_dma_cyclic()
764 return vchan_tx_prep(&tdc->vc, &desc->vd, flags); in tegra_adma_prep_dma_cyclic()
772 ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc); in tegra_adma_alloc_chan_resources()
781 free_irq(tdc->irq, tdc); in tegra_adma_alloc_chan_resources()
785 dma_cookie_init(&tdc->vc.chan); in tegra_adma_alloc_chan_resources()
795 vchan_free_chan_resources(&tdc->vc); in tegra_adma_free_chan_resources()
796 tasklet_kill(&tdc->vc.task); in tegra_adma_free_chan_resources()
797 free_irq(tdc->irq, tdc); in tegra_adma_free_chan_resources()
800 tdc->sreq_index = 0; in tegra_adma_free_chan_resources()
801 tdc->sreq_dir = DMA_TRANS_NONE; in tegra_adma_free_chan_resources()
807 struct tegra_adma *tdma = ofdma->of_dma_data; in tegra_dma_of_xlate()
812 if (dma_spec->args_count != 1) in tegra_dma_of_xlate()
815 sreq_index = dma_spec->args[0]; in tegra_dma_of_xlate()
818 dev_err(tdma->dev, "DMA request must not be 0\n"); in tegra_dma_of_xlate()
822 chan = dma_get_any_slave_channel(&tdma->dma_dev); in tegra_dma_of_xlate()
827 tdc->sreq_index = sreq_index; in tegra_dma_of_xlate()
839 if (tdma->base_addr) in tegra_adma_runtime_suspend()
840 tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); in tegra_adma_runtime_suspend()
842 if (!tdma->global_cmd) in tegra_adma_runtime_suspend()
845 for (i = 0; i < tdma->nr_channels; i++) { in tegra_adma_runtime_suspend()
846 tdc = &tdma->channels[i]; in tegra_adma_runtime_suspend()
848 if (!tdc->tdma) in tegra_adma_runtime_suspend()
851 ch_reg = &tdc->ch_regs; in tegra_adma_runtime_suspend()
852 ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD); in tegra_adma_runtime_suspend()
854 if (!ch_reg->cmd) in tegra_adma_runtime_suspend()
856 ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC - tdma->cdata->ch_tc_offset_diff); in tegra_adma_runtime_suspend()
857 ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR - in tegra_adma_runtime_suspend()
858 tdma->cdata->ch_tc_offset_diff); in tegra_adma_runtime_suspend()
859 ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR - in tegra_adma_runtime_suspend()
860 tdma->cdata->ch_tc_offset_diff); in tegra_adma_runtime_suspend()
861 ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); in tegra_adma_runtime_suspend()
863 if (tdc->global_ch_config_offset) in tegra_adma_runtime_suspend()
864 ch_reg->global_config = tdma_read(tdc->tdma, tdc->global_ch_config_offset); in tegra_adma_runtime_suspend()
866 if (!tdc->tdma->cdata->global_ch_fifo_base) in tegra_adma_runtime_suspend()
867 ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL); in tegra_adma_runtime_suspend()
868 else if (tdc->global_ch_fifo_offset) in tegra_adma_runtime_suspend()
869 ch_reg->fifo_ctrl = tdma_read(tdc->tdma, tdc->global_ch_fifo_offset); in tegra_adma_runtime_suspend()
871 ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG); in tegra_adma_runtime_suspend()
876 clk_disable_unprepare(tdma->ahub_clk); in tegra_adma_runtime_suspend()
888 ret = clk_prepare_enable(tdma->ahub_clk); in tegra_adma_runtime_resume()
893 if (tdma->base_addr) { in tegra_adma_runtime_resume()
894 tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); in tegra_adma_runtime_resume()
895 if (tdma->cdata->set_global_pg_config) in tegra_adma_runtime_resume()
896 tdma->cdata->set_global_pg_config(tdma); in tegra_adma_runtime_resume()
899 if (!tdma->global_cmd) in tegra_adma_runtime_resume()
902 for (i = 0; i < tdma->nr_channels; i++) { in tegra_adma_runtime_resume()
903 tdc = &tdma->channels[i]; in tegra_adma_runtime_resume()
905 if (!tdc->tdma) in tegra_adma_runtime_resume()
907 ch_reg = &tdc->ch_regs; in tegra_adma_runtime_resume()
909 if (!ch_reg->cmd) in tegra_adma_runtime_resume()
911 tdma_ch_write(tdc, ADMA_CH_TC - tdma->cdata->ch_tc_offset_diff, ch_reg->tc); in tegra_adma_runtime_resume()
912 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR - tdma->cdata->ch_tc_offset_diff, in tegra_adma_runtime_resume()
913 ch_reg->src_addr); in tegra_adma_runtime_resume()
914 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR - tdma->cdata->ch_tc_offset_diff, in tegra_adma_runtime_resume()
915 ch_reg->trg_addr); in tegra_adma_runtime_resume()
916 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl); in tegra_adma_runtime_resume()
918 if (!tdc->tdma->cdata->global_ch_fifo_base) in tegra_adma_runtime_resume()
919 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl); in tegra_adma_runtime_resume()
920 else if (tdc->global_ch_fifo_offset) in tegra_adma_runtime_resume()
921 tdma_write(tdc->tdma, tdc->global_ch_fifo_offset, ch_reg->fifo_ctrl); in tegra_adma_runtime_resume()
923 if (tdc->global_ch_config_offset) in tegra_adma_runtime_resume()
924 tdma_write(tdc->tdma, tdc->global_ch_config_offset, ch_reg->global_config); in tegra_adma_runtime_resume()
926 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config); in tegra_adma_runtime_resume()
928 tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd); in tegra_adma_runtime_resume()
1009 { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
1010 { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data },
1011 { .compatible = "nvidia,tegra264-adma", .data = &tegra264_chip_data },
1023 cdata = of_device_get_match_data(&pdev->dev); in tegra_adma_probe()
1025 dev_err(&pdev->dev, "device match data not found\n"); in tegra_adma_probe()
1026 return -ENODEV; in tegra_adma_probe()
1029 tdma = devm_kzalloc(&pdev->dev, in tegra_adma_probe()
1030 struct_size(tdma, channels, cdata->nr_channels), in tegra_adma_probe()
1033 return -ENOMEM; in tegra_adma_probe()
1035 tdma->dev = &pdev->dev; in tegra_adma_probe()
1036 tdma->cdata = cdata; in tegra_adma_probe()
1037 tdma->nr_channels = cdata->nr_channels; in tegra_adma_probe()
1042 tdma->ch_base_addr = devm_ioremap_resource(&pdev->dev, res_page); in tegra_adma_probe()
1043 if (IS_ERR(tdma->ch_base_addr)) in tegra_adma_probe()
1044 return PTR_ERR(tdma->ch_base_addr); in tegra_adma_probe()
1051 if (res_page->start < res_base->start) in tegra_adma_probe()
1052 return -EINVAL; in tegra_adma_probe()
1053 page_offset = res_page->start - res_base->start; in tegra_adma_probe()
1054 ch_base_offset = cdata->ch_base_offset; in tegra_adma_probe()
1056 return -EINVAL; in tegra_adma_probe()
1060 return -EINVAL; in tegra_adma_probe()
1062 tdma->ch_page_no = page_no - 1; in tegra_adma_probe()
1063 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res_base); in tegra_adma_probe()
1064 if (IS_ERR(tdma->base_addr)) in tegra_adma_probe()
1065 return PTR_ERR(tdma->base_addr); in tegra_adma_probe()
1071 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res_base); in tegra_adma_probe()
1072 if (IS_ERR(tdma->base_addr)) in tegra_adma_probe()
1073 return PTR_ERR(tdma->base_addr); in tegra_adma_probe()
1075 return -ENODEV; in tegra_adma_probe()
1078 tdma->ch_base_addr = tdma->base_addr + cdata->ch_base_offset; in tegra_adma_probe()
1081 tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio"); in tegra_adma_probe()
1082 if (IS_ERR(tdma->ahub_clk)) { in tegra_adma_probe()
1083 dev_err(&pdev->dev, "Error: Missing ahub controller clock\n"); in tegra_adma_probe()
1084 return PTR_ERR(tdma->ahub_clk); in tegra_adma_probe()
1087 tdma->dma_chan_mask = devm_kzalloc(&pdev->dev, in tegra_adma_probe()
1088 BITS_TO_LONGS(tdma->nr_channels) * sizeof(unsigned long), in tegra_adma_probe()
1090 if (!tdma->dma_chan_mask) in tegra_adma_probe()
1091 return -ENOMEM; in tegra_adma_probe()
1094 bitmap_fill(tdma->dma_chan_mask, tdma->nr_channels); in tegra_adma_probe()
1096 ret = of_property_read_u32_array(pdev->dev.of_node, "dma-channel-mask", in tegra_adma_probe()
1097 (u32 *)tdma->dma_chan_mask, in tegra_adma_probe()
1098 BITS_TO_U32(tdma->nr_channels)); in tegra_adma_probe()
1099 if (ret < 0 && (ret != -EINVAL)) { in tegra_adma_probe()
1100 dev_err(&pdev->dev, "dma-channel-mask is not complete.\n"); in tegra_adma_probe()
1104 INIT_LIST_HEAD(&tdma->dma_dev.channels); in tegra_adma_probe()
1105 for (i = 0; i < tdma->nr_channels; i++) { in tegra_adma_probe()
1106 struct tegra_adma_chan *tdc = &tdma->channels[i]; in tegra_adma_probe()
1109 if (!test_bit(i, tdma->dma_chan_mask)) in tegra_adma_probe()
1112 tdc->chan_addr = tdma->ch_base_addr + (cdata->ch_reg_size * i); in tegra_adma_probe()
1114 if (tdma->base_addr) { in tegra_adma_probe()
1115 if (cdata->global_ch_fifo_base) in tegra_adma_probe()
1116 tdc->global_ch_fifo_offset = cdata->global_ch_fifo_base + (4 * i); in tegra_adma_probe()
1118 if (cdata->global_ch_config_base) in tegra_adma_probe()
1119 tdc->global_ch_config_offset = in tegra_adma_probe()
1120 cdata->global_ch_config_base + (4 * i); in tegra_adma_probe()
1123 tdc->irq = of_irq_get(pdev->dev.of_node, i); in tegra_adma_probe()
1124 if (tdc->irq <= 0) { in tegra_adma_probe()
1125 ret = tdc->irq ?: -ENXIO; in tegra_adma_probe()
1129 vchan_init(&tdc->vc, &tdma->dma_dev); in tegra_adma_probe()
1130 tdc->vc.desc_free = tegra_adma_desc_free; in tegra_adma_probe()
1131 tdc->tdma = tdma; in tegra_adma_probe()
1134 pm_runtime_enable(&pdev->dev); in tegra_adma_probe()
1136 ret = pm_runtime_resume_and_get(&pdev->dev); in tegra_adma_probe()
1144 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); in tegra_adma_probe()
1145 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); in tegra_adma_probe()
1146 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); in tegra_adma_probe()
1148 tdma->dma_dev.dev = &pdev->dev; in tegra_adma_probe()
1149 tdma->dma_dev.device_alloc_chan_resources = in tegra_adma_probe()
1151 tdma->dma_dev.device_free_chan_resources = in tegra_adma_probe()
1153 tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending; in tegra_adma_probe()
1154 tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic; in tegra_adma_probe()
1155 tdma->dma_dev.device_config = tegra_adma_slave_config; in tegra_adma_probe()
1156 tdma->dma_dev.device_tx_status = tegra_adma_tx_status; in tegra_adma_probe()
1157 tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all; in tegra_adma_probe()
1158 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); in tegra_adma_probe()
1159 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); in tegra_adma_probe()
1160 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in tegra_adma_probe()
1161 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in tegra_adma_probe()
1162 tdma->dma_dev.device_pause = tegra_adma_pause; in tegra_adma_probe()
1163 tdma->dma_dev.device_resume = tegra_adma_resume; in tegra_adma_probe()
1165 ret = dma_async_device_register(&tdma->dma_dev); in tegra_adma_probe()
1167 dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret); in tegra_adma_probe()
1171 ret = of_dma_controller_register(pdev->dev.of_node, in tegra_adma_probe()
1174 dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret); in tegra_adma_probe()
1178 pm_runtime_put(&pdev->dev); in tegra_adma_probe()
1180 dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n", in tegra_adma_probe()
1181 tdma->nr_channels); in tegra_adma_probe()
1186 dma_async_device_unregister(&tdma->dma_dev); in tegra_adma_probe()
1188 pm_runtime_put_sync(&pdev->dev); in tegra_adma_probe()
1190 pm_runtime_disable(&pdev->dev); in tegra_adma_probe()
1192 while (--i >= 0) in tegra_adma_probe()
1193 irq_dispose_mapping(tdma->channels[i].irq); in tegra_adma_probe()
1203 of_dma_controller_free(pdev->dev.of_node); in tegra_adma_remove()
1204 dma_async_device_unregister(&tdma->dma_dev); in tegra_adma_remove()
1206 for (i = 0; i < tdma->nr_channels; ++i) { in tegra_adma_remove()
1207 if (tdma->channels[i].irq) in tegra_adma_remove()
1208 irq_dispose_mapping(tdma->channels[i].irq); in tegra_adma_remove()
1211 pm_runtime_disable(&pdev->dev); in tegra_adma_remove()
1223 .name = "tegra-adma",
1233 MODULE_ALIAS("platform:tegra210-adma");