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Searched +full:tegra20 +full:- +full:ahb (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,tegra20-ahb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-ahb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
11 title: NVIDIA Tegra AHB
16 - enum:
17 - nvidia,tegra20-ahb
18 - nvidia,tegra30-ahb
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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
9 #include "tegra20-peripherals-opp.dtsi"
12 compatible = "nvidia,tegra20";
13 interrupt-parent = <&lic>;
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H A Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
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H A Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
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/linux/drivers/amba/
H A Dtegra-ahb.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <soc/tegra/ahb.h>
23 #define DRV_NAME "tegra-ahb"
79 * 0x4 for the AHB IP block. According to the TRM, the low byte
81 * whether the passed-in physical address is incorrect, and if so, to
126 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset) in gizmo_readl() argument
128 return readl(ahb->regs + offset); in gizmo_readl()
131 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset) in gizmo_writel() argument
133 writel(value, ahb->regs + offset); in gizmo_writel()
141 struct tegra_ahb *ahb; in tegra_ahb_enable_smmu() local
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/linux/drivers/rtc/
H A Drtc-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2010-2019, NVIDIA Corporation.
21 /* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
58 * RTC hardware is busy when it is updating its values over AHB once every
64 return readl(info->base + TEGRA_RTC_REG_BUSY) & 1; in tegra_rtc_check_busy()
74 * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
85 * updated seconds+msec registers to AHB side. in tegra_rtc_wait_while_busy()
88 if (!retries--) in tegra_rtc_wait_while_busy()
99 return -ETIMEDOUT; in tegra_rtc_wait_while_busy()
112 spin_lock_irqsave(&info->lock, flags); in tegra_rtc_read_time()
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