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Searched +full:tegra186 +full:- +full:xusb (Results 1 – 12 of 12) sorted by relevance

/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra186-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 xHCI controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 exposed by the Tegra XUSB pad controller.
18 const: nvidia,tegra186-xusb
22 - description: base and length of the xHCI host registers
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H A Dnvidia,tegra-xudc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra XUSB device mode controller (XUDC)
14 - Nagarjuna Kristam <nkristam@nvidia.com>
15 - JC Kuo <jckuo@nvidia.com>
16 - Thierry Reding <treding@nvidia.com>
21 - enum:
22 - nvidia,tegra210-xudc # For Tegra210
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/linux/drivers/phy/tegra/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_PHY_TEGRA_XUSB) += phy-tegra-xusb.o
4 phy-tegra-xusb-y += xusb.o
5 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o
6 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o
7 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o
8 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o
9 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) += xusb-tegra186.o
10 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_234_SOC) += xusb-tegra186.o
11 obj-$(CONFIG_PHY_TEGRA194_P2U) += phy-tegra194-p2u.o
H A Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
13 #include <linux/phy/tegra/xusb.h>
22 #include "xusb.h"
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
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H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
18 #include "xusb.h"
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
31 /* XUSB PADCTL registers */
121 /* XUSB AO registers */
280 writel(value, priv->ao_regs + offset); in ao_writel()
285 return readl(priv->ao_regs + offset); in ao_readl()
304 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
306 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
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/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 XUSB pad controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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H A Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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H A Dtegra186-p3509-0000+p3636-0001.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/mfd/max77620.h>
8 #include "tegra186.dtsi"
12 compatible = "nvidia,p3509-0000+p3636-0001", "nvidia,tegra186";
30 stdout-path = "serial0:115200n8";
41 phy-reset-gpios = <&gpio_aon TEGRA186_AON_GPIO(AA, 6) GPIO_ACTIVE_LOW>;
42 phy-handle = <&phy>;
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H A Dtegra186-p2771-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra186-p3310.dtsi"
11 compatible = "nvidia,p2771-0000", "nvidia,tegra186";
23 #address-cells = <1>;
24 #size-cells = <0>;
30 remote-endpoint = <&xbar_i2s1_ep>;
38 dai-format = "i2s";
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/linux/drivers/usb/host/
H A Dxhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
11 #include <linux/dma-mapping.h>
20 #include <linux/phy/tegra/xusb.h>
321 return readl(tegra->fpci_base + offset); in fpci_readl()
327 writel(value, tegra->fpci_base + offset); in fpci_writel()
332 return readl(tegra->ipfs_base + offset); in ipfs_readl()
338 writel(value, tegra->ipfs_base + offset); in ipfs_writel()
343 return readl(tegra->bar2_base + offset); in bar2_readl()
349 writel(value, tegra->bar2_base + offset); in bar2_writel()
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/linux/drivers/usb/gadget/udc/
H A Dtegra-xudc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * NVIDIA Tegra XUSB device mode controller
5 * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/dma-mapping.h>
20 #include <linux/phy/tegra/xusb.h>
246 return (le32_to_cpu(ctx->member) >> (shift)) & (mask); \
253 tmp = le32_to_cpu(ctx->member) & ~((mask) << (shift)); \
255 ctx->member = cpu_to_le32(tmp); \
338 return (le32_to_cpu(trb->member) >> (shift)) & (mask); \
345 tmp = le32_to_cpu(trb->member) & ~((mask) << (shift)); \
[all …]