Lines Matching +full:tegra186 +full:- +full:xusb
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
13 compatible = "nvidia,tegra186";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "nvidia,tegra186-misc";
25 compatible = "nvidia,tegra186-gpio";
26 reg-names = "security", "gpio";
35 #interrupt-cells = <2>;
36 interrupt-controller;
37 #gpio-cells = <2>;
38 gpio-controller;
42 compatible = "nvidia,tegra186-eqos",
43 "snps,dwc-qos-ethernet-4.10";
60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
62 reset-names = "eqos";
65 interconnect-names = "dma-mem", "write";
69 snps,write-requests = <1>;
70 snps,read-requests = <3>;
71 snps,burst-map = <0x7>;
76 gpcdma: dma-controller@2600000 {
77 compatible = "nvidia,tegra186-gpcdma";
80 reset-names = "gpcdma";
113 #dma-cells = <1>;
115 dma-coherent;
116 dma-channel-mask = <0xfffffffe>;
121 compatible = "nvidia,tegra186-aconnect",
122 "nvidia,tegra210-aconnect";
125 clock-names = "ape", "apb2ape";
126 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
127 #address-cells = <1>;
128 #size-cells = <1>;
133 compatible = "nvidia,tegra186-ahub";
136 clock-names = "ahub";
137 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
138 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
139 assigned-clock-rates = <81600000>;
140 #address-cells = <1>;
141 #size-cells = <1>;
146 compatible = "nvidia,tegra186-i2s",
147 "nvidia,tegra210-i2s";
151 clock-names = "i2s", "sync_input";
152 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
153 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
154 assigned-clock-rates = <1536000>;
155 sound-name-prefix = "I2S1";
160 compatible = "nvidia,tegra186-i2s",
161 "nvidia,tegra210-i2s";
165 clock-names = "i2s", "sync_input";
166 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
167 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
168 assigned-clock-rates = <1536000>;
169 sound-name-prefix = "I2S2";
174 compatible = "nvidia,tegra186-i2s",
175 "nvidia,tegra210-i2s";
179 clock-names = "i2s", "sync_input";
180 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
181 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
182 assigned-clock-rates = <1536000>;
183 sound-name-prefix = "I2S3";
188 compatible = "nvidia,tegra186-i2s",
189 "nvidia,tegra210-i2s";
193 clock-names = "i2s", "sync_input";
194 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
195 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
196 assigned-clock-rates = <1536000>;
197 sound-name-prefix = "I2S4";
202 compatible = "nvidia,tegra186-i2s",
203 "nvidia,tegra210-i2s";
207 clock-names = "i2s", "sync_input";
208 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
209 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
210 assigned-clock-rates = <1536000>;
211 sound-name-prefix = "I2S5";
216 compatible = "nvidia,tegra186-i2s",
217 "nvidia,tegra210-i2s";
221 clock-names = "i2s", "sync_input";
222 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
223 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
224 assigned-clock-rates = <1536000>;
225 sound-name-prefix = "I2S6";
230 compatible = "nvidia,tegra186-sfc",
231 "nvidia,tegra210-sfc";
233 sound-name-prefix = "SFC1";
238 compatible = "nvidia,tegra186-sfc",
239 "nvidia,tegra210-sfc";
241 sound-name-prefix = "SFC2";
246 compatible = "nvidia,tegra186-sfc",
247 "nvidia,tegra210-sfc";
249 sound-name-prefix = "SFC3";
254 compatible = "nvidia,tegra186-sfc",
255 "nvidia,tegra210-sfc";
257 sound-name-prefix = "SFC4";
262 compatible = "nvidia,tegra186-amx",
263 "nvidia,tegra210-amx";
265 sound-name-prefix = "AMX1";
270 compatible = "nvidia,tegra186-amx",
271 "nvidia,tegra210-amx";
273 sound-name-prefix = "AMX2";
278 compatible = "nvidia,tegra186-amx",
279 "nvidia,tegra210-amx";
281 sound-name-prefix = "AMX3";
286 compatible = "nvidia,tegra186-amx",
287 "nvidia,tegra210-amx";
289 sound-name-prefix = "AMX4";
294 compatible = "nvidia,tegra186-adx",
295 "nvidia,tegra210-adx";
297 sound-name-prefix = "ADX1";
302 compatible = "nvidia,tegra186-adx",
303 "nvidia,tegra210-adx";
305 sound-name-prefix = "ADX2";
310 compatible = "nvidia,tegra186-adx",
311 "nvidia,tegra210-adx";
313 sound-name-prefix = "ADX3";
318 compatible = "nvidia,tegra186-adx",
319 "nvidia,tegra210-adx";
321 sound-name-prefix = "ADX4";
326 compatible = "nvidia,tegra210-dmic";
329 clock-names = "dmic";
330 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
331 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
332 assigned-clock-rates = <3072000>;
333 sound-name-prefix = "DMIC1";
338 compatible = "nvidia,tegra210-dmic";
341 clock-names = "dmic";
342 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
343 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
344 assigned-clock-rates = <3072000>;
345 sound-name-prefix = "DMIC2";
350 compatible = "nvidia,tegra210-dmic";
353 clock-names = "dmic";
354 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
355 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
356 assigned-clock-rates = <3072000>;
357 sound-name-prefix = "DMIC3";
362 compatible = "nvidia,tegra210-dmic";
365 clock-names = "dmic";
366 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
367 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
368 assigned-clock-rates = <3072000>;
369 sound-name-prefix = "DMIC4";
374 compatible = "nvidia,tegra186-dspk";
377 clock-names = "dspk";
378 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
379 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
380 assigned-clock-rates = <12288000>;
381 sound-name-prefix = "DSPK1";
386 compatible = "nvidia,tegra186-dspk";
389 clock-names = "dspk";
390 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
391 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
392 assigned-clock-rates = <12288000>;
393 sound-name-prefix = "DSPK2";
397 tegra_ope1: processing-engine@2908000 {
398 compatible = "nvidia,tegra186-ope",
399 "nvidia,tegra210-ope";
401 #address-cells = <1>;
402 #size-cells = <1>;
404 sound-name-prefix = "OPE1";
408 compatible = "nvidia,tegra186-peq",
409 "nvidia,tegra210-peq";
413 dynamic-range-compressor@2908200 {
414 compatible = "nvidia,tegra186-mbdrc",
415 "nvidia,tegra210-mbdrc";
421 compatible = "nvidia,tegra186-mvc",
422 "nvidia,tegra210-mvc";
424 sound-name-prefix = "MVC1";
429 compatible = "nvidia,tegra186-mvc",
430 "nvidia,tegra210-mvc";
432 sound-name-prefix = "MVC2";
437 compatible = "nvidia,tegra186-amixer",
438 "nvidia,tegra210-amixer";
440 sound-name-prefix = "MIXER1";
445 compatible = "nvidia,tegra186-admaif";
467 dma-names = "rx1", "tx1",
491 compatible = "nvidia,tegra186-asrc";
493 sound-name-prefix = "ASRC1";
498 adma: dma-controller@2930000 {
499 compatible = "nvidia,tegra186-adma";
501 interrupt-parent = <&agic>;
534 #dma-cells = <1>;
536 clock-names = "d_audio";
540 agic: interrupt-controller@2a40000 {
541 compatible = "nvidia,tegra186-agic",
542 "nvidia,tegra210-agic";
543 #interrupt-cells = <3>;
544 interrupt-controller;
550 clock-names = "clk";
555 mc: memory-controller@2c00000 {
556 compatible = "nvidia,tegra186-mc";
557 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
563 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
567 #interconnect-cells = <1>;
568 #address-cells = <2>;
569 #size-cells = <2>;
577 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
579 emc: external-memory-controller@2c60000 {
580 compatible = "nvidia,tegra186-emc";
584 clock-names = "emc";
586 #interconnect-cells = <0>;
593 compatible = "nvidia,tegra186-timer";
609 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
611 reg-shift = <2>;
619 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
621 reg-shift = <2>;
624 clock-names = "serial";
626 reset-names = "serial";
631 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
633 reg-shift = <2>;
636 clock-names = "serial";
638 reset-names = "serial";
643 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
645 reg-shift = <2>;
648 clock-names = "serial";
650 reset-names = "serial";
655 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
657 reg-shift = <2>;
660 clock-names = "serial";
662 reset-names = "serial";
667 compatible = "nvidia,tegra186-i2c";
670 #address-cells = <1>;
671 #size-cells = <0>;
673 clock-names = "div-clk";
675 reset-names = "i2c";
677 dma-names = "rx", "tx";
682 compatible = "nvidia,tegra186-i2c";
685 #address-cells = <1>;
686 #size-cells = <0>;
688 clock-names = "div-clk";
690 reset-names = "i2c";
692 dma-names = "rx", "tx";
698 compatible = "nvidia,tegra186-i2c";
701 #address-cells = <1>;
702 #size-cells = <0>;
704 clock-names = "div-clk";
706 reset-names = "i2c";
707 pinctrl-names = "default", "idle";
708 pinctrl-0 = <&state_dpaux1_i2c>;
709 pinctrl-1 = <&state_dpaux1_off>;
711 dma-names = "rx", "tx";
717 compatible = "nvidia,tegra186-i2c";
720 #address-cells = <1>;
721 #size-cells = <0>;
723 clock-names = "div-clk";
725 reset-names = "i2c";
731 compatible = "nvidia,tegra186-i2c";
734 #address-cells = <1>;
735 #size-cells = <0>;
737 clock-names = "div-clk";
739 reset-names = "i2c";
740 pinctrl-names = "default", "idle";
741 pinctrl-0 = <&state_dpaux_i2c>;
742 pinctrl-1 = <&state_dpaux_off>;
744 dma-names = "rx", "tx";
749 compatible = "nvidia,tegra186-i2c";
752 #address-cells = <1>;
753 #size-cells = <0>;
755 clock-names = "div-clk";
757 reset-names = "i2c";
759 dma-names = "rx", "tx";
764 compatible = "nvidia,tegra186-i2c";
767 #address-cells = <1>;
768 #size-cells = <0>;
770 clock-names = "div-clk";
772 reset-names = "i2c";
774 dma-names = "rx", "tx";
779 compatible = "nvidia,tegra186-pwm";
783 reset-names = "pwm";
785 #pwm-cells = <2>;
789 compatible = "nvidia,tegra186-pwm";
793 reset-names = "pwm";
795 #pwm-cells = <2>;
799 compatible = "nvidia,tegra186-pwm";
803 reset-names = "pwm";
805 #pwm-cells = <2>;
809 compatible = "nvidia,tegra186-pwm";
813 reset-names = "pwm";
815 #pwm-cells = <2>;
819 compatible = "nvidia,tegra186-pwm";
823 reset-names = "pwm";
825 #pwm-cells = <2>;
829 compatible = "nvidia,tegra186-pwm";
833 reset-names = "pwm";
835 #pwm-cells = <2>;
839 compatible = "nvidia,tegra186-pwm";
843 reset-names = "pwm";
845 #pwm-cells = <2>;
849 compatible = "nvidia,tegra186-sdhci";
854 clock-names = "sdhci", "tmclk";
856 reset-names = "sdhci";
859 interconnect-names = "dma-mem", "write";
861 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
862 pinctrl-0 = <&sdmmc1_3v3>;
863 pinctrl-1 = <&sdmmc1_1v8>;
864 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
865 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
866 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
867 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
868 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
869 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
870 nvidia,default-tap = <0x5>;
871 nvidia,default-trim = <0xb>;
872 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
874 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
879 compatible = "nvidia,tegra186-sdhci";
884 clock-names = "sdhci", "tmclk";
886 reset-names = "sdhci";
889 interconnect-names = "dma-mem", "write";
891 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
892 pinctrl-0 = <&sdmmc2_3v3>;
893 pinctrl-1 = <&sdmmc2_1v8>;
894 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
895 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
896 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
897 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
898 nvidia,default-tap = <0x5>;
899 nvidia,default-trim = <0xb>;
904 compatible = "nvidia,tegra186-sdhci";
909 clock-names = "sdhci", "tmclk";
911 reset-names = "sdhci";
914 interconnect-names = "dma-mem", "write";
916 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
917 pinctrl-0 = <&sdmmc3_3v3>;
918 pinctrl-1 = <&sdmmc3_1v8>;
919 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
920 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
921 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
922 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
923 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
924 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
925 nvidia,default-tap = <0x5>;
926 nvidia,default-trim = <0xb>;
931 compatible = "nvidia,tegra186-sdhci";
936 clock-names = "sdhci", "tmclk";
937 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
939 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
941 reset-names = "sdhci";
944 interconnect-names = "dma-mem", "write";
946 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
947 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
948 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
949 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
950 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
951 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
952 nvidia,default-tap = <0x9>;
953 nvidia,default-trim = <0x5>;
954 nvidia,dqs-trim = <63>;
955 mmc-hs400-1_8v;
956 supports-cqe;
961 compatible = "nvidia,tegra186-ahci";
967 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
970 interconnect-names = "dma-mem", "write";
975 clock-names = "sata", "sata-oob";
976 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
978 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
980 assigned-clock-rates = <102000000>,
984 reset-names = "sata", "sata-cold";
989 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
995 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
999 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1000 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1003 interconnect-names = "dma-mem", "write";
1009 compatible = "nvidia,tegra186-xusb-padctl";
1012 reg-names = "padctl", "ao";
1016 reset-names = "padctl";
1023 clock-names = "trk";
1027 usb2-0 {
1029 #phy-cells = <0>;
1032 usb2-1 {
1034 #phy-cells = <0>;
1037 usb2-2 {
1039 #phy-cells = <0>;
1046 clock-names = "trk";
1050 hsic-0 {
1052 #phy-cells = <0>;
1061 usb3-0 {
1063 #phy-cells = <0>;
1066 usb3-1 {
1068 #phy-cells = <0>;
1071 usb3-2 {
1073 #phy-cells = <0>;
1080 usb2-0 {
1084 usb2-1 {
1088 usb2-2 {
1092 hsic-0 {
1096 usb3-0 {
1100 usb3-1 {
1104 usb3-2 {
1111 compatible = "nvidia,tegra186-xusb";
1114 reg-names = "hcd", "fpci";
1126 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
1129 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
1131 power-domain-names = "xusb_host", "xusb_ss";
1134 interconnect-names = "dma-mem", "write";
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1140 nvidia,xusb-padctl = <&padctl>;
1144 compatible = "nvidia,tegra186-xudc";
1147 reg-names = "base", "fpci";
1153 clock-names = "dev", "ss", "ss_src", "fs_src";
1156 interconnect-names = "dma-mem", "write";
1158 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
1160 power-domain-names = "dev", "ss";
1161 nvidia,xusb-padctl = <&padctl>;
1166 compatible = "nvidia,tegra186-efuse";
1169 clock-names = "fuse";
1172 gic: interrupt-controller@3881000 {
1173 compatible = "arm,gic-400";
1174 #interrupt-cells = <3>;
1175 interrupt-controller;
1182 interrupt-parent = <&gic>;
1186 compatible = "nvidia,tegra186-cec";
1190 clock-names = "cec";
1195 compatible = "nvidia,tegra186-hsp";
1198 interrupt-names = "doorbell";
1199 #mbox-cells = <2>;
1204 compatible = "nvidia,tegra186-i2c";
1207 #address-cells = <1>;
1208 #size-cells = <0>;
1210 clock-names = "div-clk";
1212 reset-names = "i2c";
1214 dma-names = "rx", "tx";
1219 compatible = "nvidia,tegra186-i2c";
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1225 clock-names = "div-clk";
1227 reset-names = "i2c";
1229 dma-names = "rx", "tx";
1234 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1236 reg-shift = <2>;
1239 clock-names = "serial";
1241 reset-names = "serial";
1246 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1248 reg-shift = <2>;
1251 clock-names = "serial";
1253 reset-names = "serial";
1258 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
1260 interrupt-parent = <&pmc>;
1263 clock-names = "rtc";
1268 compatible = "nvidia,tegra186-gpio-aon";
1269 reg-names = "security", "gpio";
1273 gpio-controller;
1274 #gpio-cells = <2>;
1275 interrupt-controller;
1276 #interrupt-cells = <2>;
1280 compatible = "nvidia,tegra186-pwm";
1284 reset-names = "pwm";
1286 #pwm-cells = <2>;
1290 compatible = "nvidia,tegra186-pmc";
1295 reg-names = "pmc", "wake", "aotag", "scratch";
1297 #interrupt-cells = <2>;
1298 interrupt-controller;
1300 sdmmc1_1v8: sdmmc1-1v8 {
1301 pins = "sdmmc1-hv";
1302 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1305 sdmmc1_3v3: sdmmc1-3v3 {
1306 pins = "sdmmc1-hv";
1307 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1310 sdmmc2_1v8: sdmmc2-1v8 {
1311 pins = "sdmmc2-hv";
1312 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1315 sdmmc2_3v3: sdmmc2-3v3 {
1316 pins = "sdmmc2-hv";
1317 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1320 sdmmc3_1v8: sdmmc3-1v8 {
1321 pins = "sdmmc3-hv";
1322 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1325 sdmmc3_3v3: sdmmc3-3v3 {
1326 pins = "sdmmc3-hv";
1327 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1332 compatible = "nvidia,tegra186-ccplex-cluster";
1339 compatible = "nvidia,tegra186-pcie";
1340 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1345 reg-names = "pads", "afi", "cs";
1349 interrupt-names = "intr", "msi";
1351 #interrupt-cells = <1>;
1352 interrupt-map-mask = <0 0 0 0>;
1353 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1355 bus-range = <0x00 0xff>;
1356 #address-cells = <3>;
1357 #size-cells = <2>;
1363 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1369 clock-names = "pex", "afi", "pll_e";
1374 reset-names = "pex", "afi", "pcie_x";
1378 interconnect-names = "dma-mem", "write";
1381 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1382 iommu-map-mask = <0x0>;
1388 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1392 #address-cells = <3>;
1393 #size-cells = <2>;
1396 nvidia,num-lanes = <2>;
1401 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1405 #address-cells = <3>;
1406 #size-cells = <2>;
1409 nvidia,num-lanes = <1>;
1414 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1418 #address-cells = <3>;
1419 #size-cells = <2>;
1422 nvidia,num-lanes = <1>;
1427 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
1494 stream-match-mask = <0x7f80>;
1495 #global-interrupts = <1>;
1496 #iommu-cells = <1>;
1498 nvidia,memory-controller = <&mc>;
1502 compatible = "nvidia,tegra186-host1x";
1505 reg-names = "hypervisor", "vm";
1508 interrupt-names = "syncpt", "host1x";
1510 clock-names = "host1x";
1512 reset-names = "host1x";
1514 #address-cells = <1>;
1515 #size-cells = <1>;
1520 interconnect-names = "dma-mem";
1525 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>,
1535 compatible = "nvidia,tegra186-dpaux";
1540 clock-names = "dpaux", "parent";
1542 reset-names = "dpaux";
1545 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1547 state_dpaux1_aux: pinmux-aux {
1548 groups = "dpaux-io";
1552 state_dpaux1_i2c: pinmux-i2c {
1553 groups = "dpaux-io";
1557 state_dpaux1_off: pinmux-off {
1558 groups = "dpaux-io";
1562 i2c-bus {
1563 #address-cells = <1>;
1564 #size-cells = <0>;
1568 display-hub@15200000 {
1569 compatible = "nvidia,tegra186-display";
1578 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1583 clock-names = "disp", "dsc", "hub";
1586 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1588 #address-cells = <1>;
1589 #size-cells = <1>;
1594 compatible = "nvidia,tegra186-dc";
1598 clock-names = "dc";
1600 reset-names = "dc";
1602 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1605 interconnect-names = "dma-mem", "read-1";
1613 compatible = "nvidia,tegra186-dc";
1617 clock-names = "dc";
1619 reset-names = "dc";
1621 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1624 interconnect-names = "dma-mem", "read-1";
1632 compatible = "nvidia,tegra186-dc";
1636 clock-names = "dc";
1638 reset-names = "dc";
1640 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1643 interconnect-names = "dma-mem", "read-1";
1652 compatible = "nvidia,tegra186-dsi";
1658 clock-names = "dsi", "lp", "parent";
1660 reset-names = "dsi";
1663 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1667 compatible = "nvidia,tegra186-vic";
1671 clock-names = "vic";
1673 reset-names = "vic";
1675 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1678 interconnect-names = "dma-mem", "write";
1683 compatible = "nvidia,tegra186-nvjpg";
1686 clock-names = "nvjpg";
1688 reset-names = "nvjpg";
1690 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
1693 interconnect-names = "dma-mem", "write";
1698 compatible = "nvidia,tegra186-dsi";
1704 clock-names = "dsi", "lp", "parent";
1706 reset-names = "dsi";
1709 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1713 compatible = "nvidia,tegra186-nvdec";
1716 clock-names = "nvdec";
1718 reset-names = "nvdec";
1720 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
1724 interconnect-names = "dma-mem", "read-1", "write";
1729 compatible = "nvidia,tegra186-nvenc";
1732 clock-names = "nvenc";
1734 reset-names = "nvenc";
1736 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
1739 interconnect-names = "dma-mem", "write";
1744 compatible = "nvidia,tegra186-sor";
1753 clock-names = "sor", "out", "parent", "dp", "safe",
1756 reset-names = "sor";
1757 pinctrl-0 = <&state_dpaux_aux>;
1758 pinctrl-1 = <&state_dpaux_i2c>;
1759 pinctrl-2 = <&state_dpaux_off>;
1760 pinctrl-names = "aux", "i2c", "off";
1763 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1768 compatible = "nvidia,tegra186-sor";
1777 clock-names = "sor", "out", "parent", "dp", "safe",
1780 reset-names = "sor";
1781 pinctrl-0 = <&state_dpaux1_aux>;
1782 pinctrl-1 = <&state_dpaux1_i2c>;
1783 pinctrl-2 = <&state_dpaux1_off>;
1784 pinctrl-names = "aux", "i2c", "off";
1787 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1792 compatible = "nvidia,tegra186-dpaux";
1797 clock-names = "dpaux", "parent";
1799 reset-names = "dpaux";
1802 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1804 state_dpaux_aux: pinmux-aux {
1805 groups = "dpaux-io";
1809 state_dpaux_i2c: pinmux-i2c {
1810 groups = "dpaux-io";
1814 state_dpaux_off: pinmux-off {
1815 groups = "dpaux-io";
1819 i2c-bus {
1820 #address-cells = <1>;
1821 #size-cells = <0>;
1826 compatible = "nvidia,tegra186-dsi-padctl";
1829 reset-names = "dsi";
1834 compatible = "nvidia,tegra186-dsi";
1840 clock-names = "dsi", "lp", "parent";
1842 reset-names = "dsi";
1845 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1849 compatible = "nvidia,tegra186-dsi";
1855 clock-names = "dsi", "lp", "parent";
1857 reset-names = "dsi";
1860 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1870 interrupt-names = "stall", "nonstall";
1874 clock-names = "gpu", "pwr";
1876 reset-names = "gpu";
1879 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1884 interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1888 compatible = "nvidia,tegra186-sysram", "mmio-sram";
1890 #address-cells = <1>;
1891 #size-cells = <1>;
1893 no-memory-wc;
1897 label = "cpu-bpmp-tx";
1903 label = "cpu-bpmp-rx";
1909 compatible = "nvidia,tegra186-bpmp";
1914 interconnect-names = "read", "write", "dma-mem", "dma-write";
1919 #clock-cells = <1>;
1920 #reset-cells = <1>;
1921 #power-domain-cells = <1>;
1924 compatible = "nvidia,tegra186-bpmp-i2c";
1925 nvidia,bpmp-bus-id = <5>;
1926 #address-cells = <1>;
1927 #size-cells = <0>;
1932 compatible = "nvidia,tegra186-bpmp-thermal";
1933 #thermal-sensor-cells = <1>;
1938 #address-cells = <1>;
1939 #size-cells = <0>;
1942 compatible = "nvidia,tegra186-denver";
1944 i-cache-size = <0x20000>;
1945 i-cache-line-size = <64>;
1946 i-cache-sets = <512>;
1947 d-cache-size = <0x10000>;
1948 d-cache-line-size = <64>;
1949 d-cache-sets = <256>;
1950 next-level-cache = <&L2_DENVER>;
1955 compatible = "nvidia,tegra186-denver";
1957 i-cache-size = <0x20000>;
1958 i-cache-line-size = <64>;
1959 i-cache-sets = <512>;
1960 d-cache-size = <0x10000>;
1961 d-cache-line-size = <64>;
1962 d-cache-sets = <256>;
1963 next-level-cache = <&L2_DENVER>;
1968 compatible = "arm,cortex-a57";
1970 i-cache-size = <0xC000>;
1971 i-cache-line-size = <64>;
1972 i-cache-sets = <256>;
1973 d-cache-size = <0x8000>;
1974 d-cache-line-size = <64>;
1975 d-cache-sets = <256>;
1976 next-level-cache = <&L2_A57>;
1981 compatible = "arm,cortex-a57";
1983 i-cache-size = <0xC000>;
1984 i-cache-line-size = <64>;
1985 i-cache-sets = <256>;
1986 d-cache-size = <0x8000>;
1987 d-cache-line-size = <64>;
1988 d-cache-sets = <256>;
1989 next-level-cache = <&L2_A57>;
1994 compatible = "arm,cortex-a57";
1996 i-cache-size = <0xC000>;
1997 i-cache-line-size = <64>;
1998 i-cache-sets = <256>;
1999 d-cache-size = <0x8000>;
2000 d-cache-line-size = <64>;
2001 d-cache-sets = <256>;
2002 next-level-cache = <&L2_A57>;
2007 compatible = "arm,cortex-a57";
2009 i-cache-size = <0xC000>;
2010 i-cache-line-size = <64>;
2011 i-cache-sets = <256>;
2012 d-cache-size = <0x8000>;
2013 d-cache-line-size = <64>;
2014 d-cache-sets = <256>;
2015 next-level-cache = <&L2_A57>;
2019 L2_DENVER: l2-cache0 {
2021 cache-unified;
2022 cache-level = <2>;
2023 cache-size = <0x200000>;
2024 cache-line-size = <64>;
2025 cache-sets = <2048>;
2028 L2_A57: l2-cache1 {
2030 cache-unified;
2031 cache-level = <2>;
2032 cache-size = <0x200000>;
2033 cache-line-size = <64>;
2034 cache-sets = <2048>;
2038 pmu-a57 {
2039 compatible = "arm,cortex-a57-pmu";
2044 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
2047 pmu-denver {
2048 compatible = "nvidia,denver-pmu";
2051 interrupt-affinity = <&denver_0 &denver_1>;
2059 clock-names = "pll_a", "plla_out0";
2060 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
2063 assigned-clock-parents = <0>,
2071 assigned-clock-rates = <258000000>;
2076 thermal-zones {
2077 /* Cortex-A57 cluster */
2078 cpu-thermal {
2079 polling-delay = <0>;
2080 polling-delay-passive = <1000>;
2082 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
2092 cooling-maps {
2097 aux-thermal {
2098 polling-delay = <0>;
2099 polling-delay-passive = <1000>;
2101 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
2111 cooling-maps {
2115 gpu-thermal {
2116 polling-delay = <0>;
2117 polling-delay-passive = <1000>;
2119 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
2129 cooling-maps {
2133 pll-thermal {
2134 polling-delay = <0>;
2135 polling-delay-passive = <1000>;
2137 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
2147 cooling-maps {
2151 ao-thermal {
2152 polling-delay = <0>;
2153 polling-delay-passive = <1000>;
2155 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
2165 cooling-maps {
2171 compatible = "arm,armv8-timer";
2180 interrupt-parent = <&gic>;
2181 always-on;