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Searched +full:tegra124 +full:- +full:hdmi (Results 1 – 24 of 24) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra HDMI Output Encoder
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^hdmi@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-hdmi
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H A Dnvidia,tegra124-sor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124
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H A Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
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H A Dnvidia,tegra20-host1x.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The host1x top-level node defines a number of children, each
19 - enum:
20 - nvidia,tegra20-host1x
21 - nvidia,tegra30-host1x
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/freebsd/sys/contrib/device-tree/Bindings/media/cec/
H A Dnvidia,tegra114-cec.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/cec/nvidia,tegra114-ce
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dtegra-cec.txt1 * Tegra HDMI CEC hardware
3 The HDMI CEC module is present in Tegra SoCs and its purpose is to
4 handle communication between HDMI connected devices over the CEC bus.
7 - compatible : value should be one of the following:
8 "nvidia,tegra114-cec"
9 "nvidia,tegra124-cec"
10 "nvidia,tegra210-cec"
11 - reg : Physical base address of the IP registers and length of memory
13 - interrupts : HDMI CEC interrupt number to the CPU.
14 - clocks : from common clock binding: handle to HDMI CEC clock.
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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra124.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124
156 hdmi: hdmi@54280000 { global() label
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H A Dtegra124-apalis-v1.2-eval.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2016-2018 Toradex AG
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
9 #include "tegra124-apalis-v1.2.dtsi"
13 compatible = "toradex,apalis-tk
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H A Dtegra124-apalis-eval.dts1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
9 #include "tegra124-apalis.dtsi"
13 compatible = "toradex,apalis-tk1-eva
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H A Dtegra124-venice2.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra124.dtsi"
8 model = "NVIDIA Tegra124 Venice2";
9 compatible = "nvidia,venice2", "nvidia,tegra124";
18 stdout-path = "serial0:115200n8";
26 hdmi@54280000 {
29 vdd-supply = <&vdd_3v3_hdmi>;
30 pll-supply = <&vdd_hdmi_pll>;
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H A Dtegra124-jetson-tk1.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra124.dtsi"
7 #include "tegra124-jetson-tk1-em
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H A Dtegra124-apalis-v1.2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2016-2018 Toradex AG
6 #include "tegra124.dtsi"
7 #include "tegra124-apalis-emc.dtsi"
21 avddio-pex-suppl
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H A Dtegra124-apalis.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
6 #include "tegra124.dtsi"
7 #include "tegra124-apalis-emc.dtsi"
20 avddio-pex-suppl
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H A Dtegra124-nyan.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
4 #include "tegra124.dtsi"
14 stdout-path = "serial0:115200n8";
20 * missing a unit-address. However, the bootloader on these Chromebook
22 * Adding the unit-address causes the bootloader to create a /memory
34 /delete-node/ memory@80000000;
37 hdmi@54280000 {
40 vdd-supply = <&vdd_3v3_hdmi>;
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/freebsd/sys/arm/nvidia/tegra124/
H A Dfiles.tegra1243 # Standard tegra124 devices and support.
5 arm/nvidia/tegra124/tegra124_machdep.c standard
6 arm/nvidia/tegra124/tegra124_mp.c optional smp
7 arm/nvidia/tegra124/tegra124_car.c standard
8 arm/nvidia/tegra124/tegra124_clk_pll.c standard
9 arm/nvidia/tegra124/tegra124_clk_per.c standard
10 arm/nvidia/tegra124/tegra124_clk_super.c standard
11 arm/nvidia/tegra124/tegra124_xusbpadctl.c standard
12 arm/nvidia/tegra124/tegra124_pmc.c standard
13 arm/nvidia/tegra124/tegra124_cpufreq.c standard
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H A Dtegra124_pmc.c1 /*-
135 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
136 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
138 #define PMC_LOCK(_sc) mtx_lock(&(_sc)->mtx)
139 #define PMC_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
140 #define PMC_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
141 device_get_nameunit(_sc->dev), "tegra124_pmc", MTX_DEF)
142 #define PMC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx);
143 #define PMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED);
144 #define PMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED);
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H A Dtegra124_clk_pll.c1 /*-
38 #include <dt-bindings/clock/tegra124-car.h>
88 /* Post divider <-> register value mapping. */
417 RD4(sc, sc->base_reg, &reg); in pll_enable()
418 if (sc->type != PLL_E) in pll_enable()
421 WR4(sc, sc->base_reg, reg); in pll_enable()
430 RD4(sc, sc->base_reg, &reg); in pll_disable()
431 if (sc->type != PLL_E) in pll_disable()
434 WR4(sc, sc->base_reg, reg); in pll_disable()
443 tbl = sc->pdiv_table; in pdiv_to_reg()
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H A Dtegra124_clk_per.c1 /*-
38 #include <dt-bindings/clock/tegra124-car.h>
213 /* bank L -> 0-31 */
241 /* bank H -> 32-63 */
258 GATE(HDMI, "hdmi", "pc_hdmi", H(19)),
270 /* bank U -> 64-95 */
299 /* bank V -> 96-127 */
325 /* bank W -> 128-159*/
354 /* bank X -> 160-191*/
553 if (sc->flags & DCF_HAVE_ENA) in periph_init()
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/freebsd/sys/contrib/device-tree/Bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra132-peripherals-opp.dtsi"
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H A Dtegra132-norrin.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
9 compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124";
18 stdout-path = "serial0:115200n8";
27 hdmi@54280000 {
30 vdd-supply = <&vdd_3v3_hdmi>;
31 pll-supply = <&vdd_hdmi_pll>;
32 hdmi-supply = <&vdd_5v0_hdmi>;
34 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
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/freebsd/sys/arm/conf/
H A DGENERIC2 # GENERIC -- Generic(ish) kernel config.
7 # https://docs.freebsd.org/en/books/handbook/kernelconfig/#kernelconfig-config
26 makeoptions CONF_CFLAGS="-march=armv7a"
42 files "../nvidia/tegra124/files.tegra124"
95 device ahci # AHCI-compatible SATA controllers
129 device p2wi # Allwinner Push-Pull Two Wire
187 device axe # USB-Ethernet
188 device umass # Disks/Mass storage - Requires scbus and da
236 # IMX6 HDMI Controller
258 device imx6_snvs # IMX6 On-chip RTC
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/freebsd/sys/arm/nvidia/drm2/
H A Dtegra_hdmi.c1 /*-
53 #include <arm/nvidia/drm2/hdmi.h>
58 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v))
59 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, 4 * (_r))
205 {"nvidia,tegra124-hdmi", 1},
225 return -EINVAL; in drm_hdmi_avi_infoframe_from_display_mode()
231 if (mode->flags & DRM_MODE_FLAG_DBLCLK) in drm_hdmi_avi_infoframe_from_display_mode()
232 frame->pixel_repeat = 1; in drm_hdmi_avi_infoframe_from_display_mode()
234 frame->video_code = drm_match_cea_mode(mode); in drm_hdmi_avi_infoframe_from_display_mode()
236 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; in drm_hdmi_avi_infoframe_from_display_mode()
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