| /freebsd/crypto/krb5/src/plugins/preauth/pkinit/ |
| H A D | pkinit_matching.c | 169 rule_component *rc, *trc; in free_rule_set() local
174 trc = rc->next; in free_rule_set()
176 rc = trc; in free_rule_set()
383 rule_component *rc = NULL, *trc; in parse_rule_set() local
431 for (trc = rs->crs; trc != NULL && trc->next != NULL; trc = trc->next); in parse_rule_set()
432 if (trc == NULL) in parse_rule_set()
435 trc->next = rc; in parse_rule_set()
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/ |
| H A D | lpddr3.txt | 26 - tRC-min-tck
66 tRC-min-tck = <6>;
93 tRC = <33750>;
|
| H A D | lpddr3-timings.txt | 20 - tRC
45 tRC = <33750>;
|
| H A D | jedec,lpddr3.yaml | 87 tRC-min-tck:
205 tRC-min-tck = <6>;
230 tRC = <33750>;
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| H A D | jedec,lpddr3-timings.yaml | 64 tRC:
144 tRC = <33750>;
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| /freebsd/sys/contrib/device-tree/Bindings/ddr/ |
| H A D | lpddr3.txt | 26 - tRC-min-tck
65 tRC-min-tck = <6>;
92 tRC = <33750>;
|
| H A D | lpddr3-timings.txt | 20 - tRC
45 tRC = <33750>;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 74 unsigned Lane, const TargetRegisterClass *TRC);
97 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
133 const TargetRegisterClass *TRC) { in usesRegClass() argument
139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
141 return TRC->contains(Reg); in usesRegClass()
269 const TargetRegisterClass *TRC = in optimizeSDPattern() local
271 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
432 const TargetRegisterClass *TRC) { in createExtractSubreg() argument
433 Register Out = MRI->createVirtualRegister(TRC); in createExtractSubreg()
|
| H A D | ARMLoadStoreOptimizer.cpp | 2430 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in RescheduleOps() local
2431 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2432 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps()
3025 const TargetRegisterClass *TRC = TII->getRegClass(MCID, BaseOp, TRI, *MF); in AdjustBaseAndOffset() local
3026 MRI.constrainRegClass(NewBaseReg, TRC); in AdjustBaseAndOffset()
3082 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in createPostIncLoadStore() local
3083 MRI.constrainRegClass(NewReg, TRC); in createPostIncLoadStore()
3085 TRC = TII->getRegClass(MCID, 2, TRI, *MF); in createPostIncLoadStore()
3086 MRI.constrainRegClass(MI->getOperand(1).getReg(), TRC); in createPostIncLoadStore()
|
| H A D | ARMISelLowering.cpp | 10821 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass in SetupEntryBlockForSjLj() local
10840 Register NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10846 Register NewVReg2 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10852 Register NewVReg3 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10870 Register NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10875 Register NewVReg2 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10880 Register NewVReg3 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10885 Register NewVReg4 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10891 Register NewVReg5 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10906 Register NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kRegisterInfo.cpp | 107 const TargetRegisterClass &TRC) const { in getRegisterOrder()
108 for (unsigned i = 0; i < TRC.getNumRegs(); ++i) { in getRegisterOrder()
109 if (regsOverlap(Reg, TRC.getRegister(i))) { in getRegisterOrder()
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| H A D | M68kRegisterInfo.h | 77 int getRegisterOrder(unsigned Reg, const TargetRegisterClass &TRC) const;
|
| /freebsd/usr.sbin/lpr/lpd/ |
| H A D | printjob.c | 1488 #define TRC(q) (((q)-' ')&0177) macro
1502 d = dropit(c = TRC(cc = *sp++)); in scan_out()
1527 case TRC('_'): in dropit()
1528 case TRC(';'): in dropit()
1529 case TRC(','): in dropit()
1530 case TRC('g'): in dropit()
1531 case TRC('j'): in dropit()
1532 case TRC('p'): in dropit()
1533 case TRC('q'): in dropit()
1534 case TRC('y'): in dropit()
|
| /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | rk3399-ddr.h | 7 * DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for
|
| /freebsd/tests/sys/cddl/zfs/tests/txg_integrity/ |
| H A D | txg_integrity.d | 98 printf(">= 2: db=%x\trc=%d", (long long)args[0], args[1]);
|
| /freebsd/sys/contrib/device-tree/src/arm/ti/keystone/ |
| H A D | keystone-clocks.dtsi | 196 clock-output-names = "debugss-trc";
206 clock-output-names = "tetb-trc";
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 526 const TargetRegisterClass *TRC = in EmitSubregNode() local
545 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
551 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
565 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
682 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
684 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); in EmitRegSequence()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 1449 /// \brief Returns true if a reg:subreg pair P has a TRC class
1451 const TargetRegisterClass &TRC, in isOfRegClass() argument
1455 return RC == &TRC; in isOfRegClass()
1457 return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg); in isOfRegClass()
|
| /freebsd/sys/contrib/device-tree/src/arm/samsung/ |
| H A D | exynos5422-odroid-core.dtsi | 346 tRC-min-tck = <6>;
372 tRC = <33750>;
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 511 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
512 return TRC.getLaneMask(); in getMaxLaneMaskForVReg()
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| H A D | LiveDebugVariables.cpp | 1542 const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg); in rewriteLocations() local
1543 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize, in rewriteLocations()
1854 const TargetRegisterClass *TRC = MRI.getRegClass(Reg); in emitDebugValues() local
1857 unsigned regSizeInBits = TRI->getRegSizeInBits(*TRC); in emitDebugValues()
1865 TII->getStackSlotRange(TRC, SubReg, SpillSize, SpillOffset, *MF); in emitDebugValues()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86AvoidStoreForwardingBlocks.cpp | 557 const auto *TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, in getRegSizeInBytes() local
559 return TRI->getRegSizeInBits(*TRC) / 8; in getRegSizeInBytes()
|
| /freebsd/sys/powerpc/powerpc/ |
| H A D | db_trace.c | 247 case EXC_TRC: trapstr = "TRC"; break; in db_backtrace()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyAsmPrinter.cpp | 64 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
67 if (TRI->isTypeLegalForClass(*TRC, T)) in getRegType()
|
| /freebsd/contrib/llvm-project/clang/include/clang/AST/ |
| H A D | ASTNodeTraverser.h | 529 if (const Expr *TRC = D->getTrailingRequiresClause()) in VisitFunctionDecl() local
530 Visit(TRC); in VisitFunctionDecl()
|