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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dcirrus,lochnagar.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/cirrus,lochnagar.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of various
17 Audio system topology, clocking and power can all be controlled through
21 This binding document describes the binding for the clock portion of the
25 [1] Clock : ../clock/clock-bindings.txt
28 [2] include/dt-bindings/clock/lochnagar.h
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H A Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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H A Drenesas,emev2-smu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas EMMA Mobile EV2 System Management Unit
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
14 The System Management Unit is described in user's manual R19UH0037EJ1000_SMU.
15 This is not a clock provider, but clocks under SMU depend on it.
19 const: renesas,emev2-smu
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H A Dimx7ulp-clock.txt1 * Clock bindings for Freescale i.MX7ULP
3 i.MX7ULP Clock functions are under joint control of the System
4 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
8 and A7 domain. Except for a few clock sources shared between two
9 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
10 and and the Fast IRC clock (FIRCLK), clock sources and clock
13 M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
14 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
16 Note: this binding doc is only for A7 clock domain.
18 System Clock Generation (SCG) modules:
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H A Drenesas,emev2-smu.txt1 Device tree Clock bindings for Renesas EMMA Mobile EV2
3 This binding uses the common clock binding.
6 System Management Unit described in user's manual R19UH0037EJ1000_SMU.
7 This is not a clock provider, but clocks under SMU depend on it.
10 - compatible: Should be "renesas,emev2-smu"
11 - reg: Address and Size of SMU registers
15 "Serial clock generator" in fig."Clock System Overview" of the manual,
17 This makes internal (neither input nor output) clock that is provided
21 - compatible: Should be "renesas,emev2-smu-clkdiv"
22 - reg: Byte offset from SMU base and Bit position in the register
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H A Dsamsung,s5pv210-clock.txt1 * Samsung S5P6442/S5PC110/S5PV210 Clock Controller
3 Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
4 controller, which generates and supplies clock to various controllers
9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
26 that they are defined using standard clock bindings with following
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H A Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baika
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H A Dcanaan,k210-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/canaan,k210-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan Kendryte K210 Clock
10 - Damien Le Moal <dlemoal@kernel.org>
13 Canaan Kendryte K210 SoC clocks driver bindings. The clock
15 system controller node.
18 - dt-bindings/clock/k210-clk.h
22 const: canaan,k210-clk
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/freebsd/sys/contrib/device-tree/Bindings/ptp/
H A Dptp-qoriq.txt1 * Freescale QorIQ 1588 timer based PTP clock
5 - compatible Should be "fsl,etsec-ptp" for eTSEC
6 Should be "fsl,fman-ptp-timer" for DPAA FMan
7 Should be "fsl,dpaa2-ptp" for DPAA2
8 Should be "fsl,enetc-ptp" for ENETC
9 - reg Offset and length of the register set for the device
10 - interrupts There should be at least two interrupts. Some devices
13 Clock Properties:
15 - fsl,cksel Timer reference clock source.
16 - fsl,tclk-period Timer reference clock period in nanoseconds.
[all …]
H A Dfsl,ptp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
19 - items:
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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Daudio-graph-port.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/audio-graph-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
15 port-base:
17 - $ref: /schemas/graph.yaml#/$defs/port-base
18 - $ref: /schemas/sound/dai-params.yaml#
20 mclk-fs:
21 $ref: simple-card.yaml#/definitions/mclk-fs
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H A Dsimple-card.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-maste
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dcirrus,lochnagar.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of
17 platform. Audio system topology, clocking and power can all be
25 [2] include/dt-bindings/pinctrl/lochnagar.h
26 [3] include/dt-bindings/clock/lochnagar.h
28 And these documents for the required sub-node binding details:
29 [4] Clock: ../clock/cirrus,lochnagar.yaml
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/freebsd/sys/contrib/device-tree/Bindings/clock/sifive/
H A Dfu540-prci.txt3 On the FU540 family of SoCs, most system-wide clock and reset integration
7 - compatible: Should be "sifive,<chip>-prci". Only one value is
8 supported: "sifive,fu540-c000-prci"
9 - reg: Should describe the PRCI's register target physical address region
10 - clocks: Should point to the hfclk device tree node and the rtcclk
11 device tree node. The RTC clock here is not a time-of-day clock,
12 but is instead a high-stability clock source for system timers
14 - #clock-cells: Should be <1>
16 The clock consumer should specify the desired clock via the clock ID
17 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
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/freebsd/sys/contrib/device-tree/Bindings/arm/marvell/
H A Dap80x-system-controller.txt1 Marvell Armada AP80x System Controller
5 7K/8K/931x SoCs. It contains system controllers, which provide several
6 registers giving access to numerous features: clocks, pin-muxing and
8 these system controllers.
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
14 SYSTEM CONTROLLER 0
18 -------
21 The Device Tree node representing the AP806/AP807 system controller
24 - 0: reference clock of CPU cluster 0
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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/
H A Dbcm2712.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #address-cells = <2>;
8 #size-cells = <2>;
10 interrupt-parent = <&gicv2>;
13 /* The oscillator is the root of the clock tree. */
14 clk_osc: clk-osc {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-output-names = "osc";
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/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dfixed-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Fixed Voltage regulators
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
15 regulator.yaml, can also be used. However a fixed voltage regulator is
16 expected to have the regulator-min-microvolt and regulator-max-microvolt
20 - $ref: regulator.yaml#
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/freebsd/contrib/ntp/html/hints/
H A Dmpeix1 HP e3000 MPE/iX NTP Hints - May 29, 2001
2 ----------------------------------------
8 NTP was re-ported to MPE in May 2001. What follows are hints learned from
12 MPE lacks the clock-related APIs expected by NTP, so adjtime(), gettimeofday(),
16 Unfortunately the implementation of adjtime() has exposed a sub-second accuracy
17 bug when slewing the system time. This bug is documented in SR 5003462838, and
18 exists on all current versions of MPE. It has not been fixed at the time of
20 bug is fixed.
22 This bug has a side-effect whereby the ntpd daemon will screw up the hardware
23 PDC clock time by many minutes if used for continuous clock adjustments or in
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H A Dnotes-xntp-v311 previous versions as non-configured peers; for version-2 configured
15 <file> is the name of a statistics file." When present, each clock
23 dispersion, respectively, of the peer clock relative to the local
24 clock. About once per day the current file is closed and a new one
31 4. A driver for the TrueTime 468DC GOES Synchronized Clock is
36 Clock is included. This driver (refclock_wwvb.c) (a) does not
37 require a 1-pulse-per-second signal, (b) supports both format 0
45 7. In Version 2 special line-discipline modules were required for the
51 8. Support for an external 1-pulse-per-second (pps) signal is
54 of the pulse establishes the on-time epoch within an interval
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/freebsd/sys/contrib/device-tree/Bindings/rtc/
H A Drtc-m41t80.txt4 - compatible: should be one of:
16 - reg: I2C bus address of the device
19 - interrupts: rtc alarm interrupt.
20 - clock-output-names: From common clock binding to override the default output
21 clock name
22 - wakeup-source: Enables wake up of host system on alarm
25 - clock: Provide this if the square wave pin is used as boot-enabled fixed clock.
31 interrupt-parent = <&UIC0>;
34 clock {
35 compatible = "fixed-clock";
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/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm-cygnus-clock.dtsi34 #address-cells = <1>;
35 #size-cells = <1>;
39 #clock-cells = <0>;
40 compatible = "fixed-clock";
41 clock-frequency = <25000000>;
46 #clock-cells = <0>;
47 compatible = "brcm,cygnus-armpll";
52 /* peripheral clock for system timer */
54 #clock-cells = <0>;
55 compatible = "fixed-factor-clock";
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/freebsd/share/doc/papers/sysperf/
H A D5.t42 and revamping the lowest levels of the system
51 only by hosts at that site. To off-site hosts machines on a site's
58 The broadcast address may be set at boot time on a per-interface basis.
78 not support ARP. In addition, system managers have
85 Although the system allocates reasonable default amounts of buffering
86 for most connections, certain operations such as file system dumps
88 The \fIsetsockopt\fP system call has been extended to allow such requests.
90 are now interfaced to the protocol level allowing protocol-specific
98 32-bit words, removing the dependency on file descriptors from
101 The default per-process descriptor limit was raised from 20 to 64,
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/freebsd/lib/libpmc/
H A Dpmc.ucf.331 uncore fixed function performance counters.
37 Each fixed-function PMC measures a specific hardware event.
38 The number of fixed-function PMCs implemented in a CPU can vary.
39 The number of fixed-function PMCs present can be determined at runtime
43 Intel uncore fixed-function PMCs are documented in
45 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
46 .%T "Volume 3B: System Programming Guide, Part 2"
47 .%N "Order Number: 253669-033US"
53 Fixed-function PMCs support the following capabilities:
54 .Bl -column "PMC_CAP_INTERRUPT" "Support"
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra72-evm-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "dra7-ipu-dsp-commo
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/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt6580.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
15 interrupt-parent = <&sysirq>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
28 compatible = "arm,cortex-a7";
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