| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | socionext,uniphier-system-bus.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier System Bus
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
14 Before any access to the bus, the bus controller must be configured; the bus
16 within each bank to the CPU-viewed address. The needed setup includes the
18 be optimized for faster bus access.
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| H A D | fsl,imx8qxp-pixel-link-msi-bus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
10 - Liu Ying <victor.liu@nxp.com>
13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
14 sitting together with the PHYs. It is not the same as the MSI bus coming
15 from i.MX8 System Controller Unit (SCU) which is used to control power,
16 clock and reset through the i.MX8 Distributed Slave System Controller (DSC).
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| H A D | baikal,bt1-axi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
23 accessible by means of the Baikal-T1 System Controller.
26 - $ref: /schemas/simple-bus.yaml#
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| /freebsd/share/man/man9/ |
| H A D | bus_space.9 | 143 .Nd "bus space manipulation functions"
627 machine-independent access to bus memory and register areas.
636 For instance, a device which is mapped in one system's I/O space may be
637 mapped in memory space on a second system.
638 On a third system, architectural
640 creating a non-linear register space).
643 single system or architecture.
647 of devices on different system architectures, and to allow a single driver
648 object file to manipulate a set of devices on multiple bus types on a
653 supported by the bus.
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| H A D | device.9 | 1 .\" -*- nroff -*-
39 system such as an expansion card, the bus which that card is plugged
41 The system defines one device,
45 Normally devices representing top-level buses in
46 the system (ISA, PCI etc.) will be attached directly to
48 and other devices will be added as children of their relevant bus.
50 The devices in a system form a tree.
64 system will also have a driver (see
78 a set of bus-specific variables (see
80 and a set of driver-specific variables (see
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| /freebsd/share/man/man4/ |
| H A D | smbus.4 | 30 .Nd System Management Bus
38 system provides a uniform, modular and architecture-independent
39 system for the implementation of drivers to control various SMB devices
41 .Sh System Management Bus
43 .Em System Management Bus
44 is a two-wire interface through which simple power-related chips can communicate
45 with rest of the system.
49 A system using SMB passes messages to and from devices instead of tripping
53 system what its model/part number is, save its state for a suspend event,
57 The SMBus may share the same host device and physical bus as ACCESS bus
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| H A D | iicbus.4 | 30 .Nd I2C bus system
41 system provides a uniform, modular and architecture-independent
42 system for the implementation of drivers to control various I2C devices
45 I2C is an acronym for Inter Integrated Circuit bus.
46 The I2C bus was developed
49 easy way to connect a CPU to peripheral chips in a TV-set.
51 The BUS physically consists of 2 active wires and a ground connection.
56 Every component hooked up to the bus has its own unique address whether it
63 more BUS MASTERs.
65 The BUS MASTER is the chip issuing the commands on the BUS.
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| H A D | ppbus.4 | 30 .Nd Parallel Port Bus system
42 system provides a uniform, modular and architecture-independent
43 system for the implementation of drivers to control various parallel devices,
46 In order to write new drivers or port existing drivers, the ppbus system
48 .Bl -bullet -offset indent
50 architecture-independent macros or functions to access parallel ports
57 with kernel-in drivers.
60 The ppbus system has been designed to support the development of standard
61 and non-standard software:
63 .Bl -column "Driver" -compact
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| H A D | scsi.4 | 41 .Cd "options CAM_DEBUG_BUS=-1"
42 .Cd "options CAM_DEBUG_TARGET=-1"
43 .Cd "options CAM_DEBUG_LUN=-1"
53 subsystem provides a uniform and modular system for the implementation
67 When the system probes buses, it attaches any devices it finds to the
76 .Bl -tag -width SCSI_NO_SENSE_STRINGS
120 Do not let the "kernel bloat" zealots get to you -- leave
143 When the kernel boots, it sends a bus reset to each
149 devices need some amount of time to recover from a bus reset.
184 .Bd -literal -offset indent
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| H A D | iicmux.4 | 1 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
32 .Nd I2C bus mulitiplexer framework
37 .Bd -ragged -offset indent
44 .Bd -literal -offset indent
55 I2C bus multiplexer (mux) hardware.
64 Generally speaking, an I2C mux is connected to an upstream I2C bus, and to
66 any one of the downstream buses to the upstream bus.
75 the active downstream bus.
84 downstream bus (if any) should be connected while in the idle state.
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| H A D | gpio.4 | 2 .\" SPDX-License-Identifier: BSD-2-Clause
33 .Nd GPIO bus system
37 .Bd -ragged -offset indent
46 .Bd -ragged -offset indent
62 .Bd -ragged -offset indent
71 .Bd -ragged -offset indent
77 .Li RISC-V
79 .Bd -ragged -offset indent
85 system provides a simple interface to the GPIO pins that are usually
87 devices to the system.
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| H A D | pci.4 | 30 .Nd generic PCI/PCIe bus driver
32 To compile the PCI bus driver into the kernel,
35 .Bd -ragged -offset indent
40 .Pq SR-IOV :
41 .Bd -ragged -offset indent
45 To compile in support for native PCI-express HotPlug:
46 .Bd -ragged -offset indent
77 configuration registers, system administrators should exercise caution when
85 to modify system state if the file descriptor was opened for writing.
91 or a BAR read access could have function-specific side-effects.
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| H A D | gpioiic.4 | 30 .Nd GPIO I2C bit-banging device driver
35 .Bd -ragged -offset indent
45 .Bd -literal -offset indent
51 driver provides an IIC bit-banging interface using two GPIO pins for the
52 SCL and SDA lines on the bus.
59 They are driven to '0' or switched to input mode (Hi-Z/tri-state), and
61 other device on the bus is driving it to 0.
65 based system, such as MIPS, these values are configurable for
67 .Bl -tag -width ".Va hint.gpioiic.%d.atXXX"
77 bit-banging bus.
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| /freebsd/sys/contrib/dev/iwlwifi/ |
| H A D | iwl-drv.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2020-2021, 2023, 2025 Intel Corporation
4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
15 #define NVM_RF_CFG_DASH_MSK(x) (x & 0x3) /* bits 0-1 */
16 #define NVM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
17 #define NVM_RF_CFG_TYPE_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
18 #define NVM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
19 #define NVM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
20 #define NVM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
30 * DOC: Driver system flows - drv component
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| /freebsd/sys/contrib/edk2/Include/Protocol/ |
| H A D | PciRootBridgeIo.h | 4 PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O,
6 defferent types of bus mastering DMA.
8 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
9 SPDX-License-Identifier: BSD-2-Clause-Patent
53 /// A read operation from system memory by a bus master that is not capable of producing
58 /// A write operation from system memory by a bus master that is not capable of producing
63 /// Provides both read and write access to system memory by both the processor and a bus
68 /// A read operation from system memory by a bus master that is capable of producing PCI
73 /// A write operation to system memory by a bus master that is capable of producing PCI
78 /// Provides both read and write access to system memory by both the processor and a bus
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| H A D | DeviceIo.h | 7 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
8 SPDX-License-Identifier: BSD-2-Clause-Patent
107 /// A read operation from system memory by a bus master.
112 /// A write operation to system memory by a bus master.
117 /// Provides both read and write access to system memory
118 /// by both the processor and a bus master. The buffer is
119 /// coherent from both the processor's and the bus master's
126 Provides the device-specific addresses needed to access system memory.
129 …@param Operation Indicates if the bus master is going to read or write to system memo…
130 @param HostAddress The system memory address to map to the device.
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | baikal,bt1-ccu-div.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
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| H A D | imx7ulp-pcc-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
34 See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
40 - fsl,imx7ulp-pcc2
41 - fsl,imx7ulp-pcc3
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| /freebsd/sys/contrib/device-tree/Bindings/display/panel/ |
| H A D | panel-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
24 width-mm:
29 height-mm:
38 on the system (e.g. as an affixed label) or specified in the system's
43 non-descriptive information. For instance an LCD panel in a system that
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| /freebsd/share/doc/papers/diskperf/ |
| H A D | results.ms | 36 The first set of results is always for a file system
57 4.2BSD File Systems Tests - \fBVAX 11/750\fR
60 from an \fB8K/1K\fR 4.2BSD File System (Kbytes/sec.)
79 from \fB4K/1K\fR 4.2BSD File System (Kbytes/sec.)
115 4.2BSD File Systems Tests - \fBVAX 11/780\fR
118 from an \fB8K/1K\fR 4.2BSD File System (Kbytes/sec.)
137 from an \fB4K/1K\fR 4.2BSD File System (Kbytes/sec.)
152 tests are probably due to the file system using insufficient
157 with those of VAX 11/780s using the UDA50/RA81 storage system.
168 4.2BSD File Systems Tests - \fBDEC UDA50 - 750 vs. 780\fR
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| /freebsd/contrib/libpcap/ |
| H A D | pcap-dbus.c | 40 #include "pcap-int.h"
41 #include "pcap-dbus.h"
44 * Private data for capturing on D-Bus.
54 struct pcap_dbus *handlep = handle->priv; in dbus_read()
64 message = dbus_connection_pop_message(handlep->conn); in dbus_read()
67 /* XXX handle->opt.timeout = timeout_ms; */ in dbus_read()
68 if (!dbus_connection_read_write(handlep->conn, 100)) { in dbus_read()
69 snprintf(handle->errbuf, PCAP_ERRBUF_SIZE, "Connection closed"); in dbus_read()
70 return -1; in dbus_read()
73 if (handle->break_loop) { in dbus_read()
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| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | synopsys,dw-hdmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
16 bindings for the platform-specific integrations of the DWC HDMI TX.
26 reg-io-width:
36 - description: The bus clock for either AHB and APB
37 - description: The internal register configuration clock
40 clock-names:
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | mfd.txt | 1 Multi-Function Devices (MFD)
4 more than one non-unique yet varying hardware functionality.
8 - A mixed signal ASIC on an external bus, sometimes a PMIC (Power Management
14 - A range of memory registers containing "miscellaneous system registers" also
15 known as a system controller "syscon" or any other memory range containing a
20 - compatible : "simple-mfd" - this signifies that the operating system
23 Similarly to how "simple-bus" indicates when to see subnodes as children for
24 a simple memory-mapped bus.
27 latter case the child devices will be determined by the operating system.
29 - ranges: Describes the address mapping relationship to the parent. Should set
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | gemini.txt | 3 The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
20 - soc: the SoC should be represented by a simple bus encompassing all the
21 onchip devices, this is referred to as the soc bus node.
23 - syscon: the soc bus node must have a system controller node pointing to the
25 "cortina,gemini-syscon", "syscon";
28 - reg: syscon register location and size.
29 - #clock-cells: should be set to <1> - the system controller is also a
31 - #reset-cells: should be set to <1> - the system controller is also a
35 <dt-bindings/clock/cortina,gemini-clock.h>
38 <dt-bindings/reset/cortina,gemini-reset.h>
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| /freebsd/sys/contrib/device-tree/Bindings/iommu/ |
| H A D | samsung,sysmmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
10 - Marek Szyprowski <m.szyprowski@samsung.com>
13 Samsung's Exynos architecture contains System MMUs that enables scattered
14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
15 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
17 System MMU is an IOMMU and supports identical translation table format to
19 permissions, shareability and security protection. In addition, System MMU has
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